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1 Residual Stress in Thin Films Residual Stress EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 27 After release, poorly designed microstructures might buckle, bend, or warp often caused by residual film stress Origins of residual stress, σ Growth processes Non-equilibrium deposition Grain morphology change Gas entrapment Doping Thermal stresses Thermal expansion mismatch of materials introduce stress during cool-down after deposition Annealing Tunable Dielectric Capacitor [Yoon, et al., U. Michigan] Buckled Double-Ended Tuning Fork bending EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 28 Need to Control Film Stress Resonance frequency expression for a lateral resonator: Basic term Stress term E y = Young s modulus σ r = stress t = thickness W = beam width L = beam length M = mass Folded-beam suspension Anchor Since W «L, the stress term will dominate if σ r ~ E y Shuttle Folding truss EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 29 Tensile Versus Compressive Stress Under tensile stress, a film wants to shrink w/r to its substrate Caused, e.g., by differences in film vs. substrate thermal expansion coefficients If suspended above a substrate and anchored to it at two points, the film will be stretched by the substrate Under compressive stress, a film wants to expand w/r to its substrate If suspended above a substrate and anchored to it at two points, the film will buckle over the substrate tensile film compressive film Si-substrate Si-substrate Si-substrate Si-substrate buckled EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
2 Vertical Stress Gradients Variation of residual stress in the direction of film growth Can warp released structures in z-direction Stress in Polysilicon Films Stress depends on crystal structure, which in turn depends upon the deposition temperature Temperature 600 C Films are initially amorphous,then crystallize Get equiaxed crystals, largely isotropic Crystals have higher density tensile stress Small stress gradient Temperature 600 C Columnar crystals grow during deposition As crystals grow vertically and in-plane they push on neighbors compressive stress Positive stress gradient EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 31 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 32 Annealing Out Polysilicon Stress Control polysi stress by annealing at high temperatures Typical anneal temperatures: C Grain boundaries move, relax Can dope while annealing by sandwiching the polysilicon between similarly doped oxides (symmetric dopant drivein), e.g. using wt. % PSG Topography Issues Degradation of lithographic resolution PR step coverage, streaking Thickness differences pose problems for reduction steppers Direction of Spin PR PR PR Stringers Problematic when using anisotropic etching, e.g., RIE RIE Stringer Rapid thermal anneal (RTA) also effective (surprisingly) EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 33 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
3 Electroplating: Metal MEMS Nickel Surface-Micromachining Process Flow Photoresist Wafer Release Etchant Use electroplating to obtain metal μstructures When thick: call it LIGA Pros: fast low temp deposition, very conductive Cons: drift, low mech. Q but may be solvable? Electrode Suspended Nickel Microstructure Nickel Ti/Au EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 35 Si 3 N 4 Isolation EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 36 Nickel Metal Surface-Micromachining Nickel Metal Surface-Micromachining Oxide Photoresist Titanium Titanium Gold Gold Deposit isolation LTO: Target = 2μm 1 hr. 40 min. o C Densify the LTO o C for 30 min. Define metal interconnect via lift-off Spin photoresist and pattern lithographically to open areas where interconnect will stay Evaporate a Ti/Au layer Target = 30nm Ti Target = 270nm Au Remove photoresist in PRS2000 Ti/Au atop the photoresist also removed EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 37 Photoresist Evaporate Al to serve as a sacrificial layer Target = 1μm Lithography to define anchor openings Wet etch the aluminum to form anchor vias Use solution of H 3 PO 4 /HNO 3 /H 2 O Remove photoresist in PRS2000 Electroplate nickel to fill the anchor vias Use solution of nickel 50 C Time the electroplating to planarize the surface EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
4 Nickel Metal Surface-Micromachining Nickel Metal Surface-Micromachining Nickel seed layer Photoresist Electroplated Nickel Evaporate a thin film of nickel to serve as a seed layer for subsequent Ni electroplating Target = 20nm Form a photoresist mold for subsequent electroplating Spin 6 um-thick AZ 9260 photoresist Lithographically pattern the photoresist to delineate areas where nickel structures are to be formed Electroplate nickel structural material through the PR mold Use a solution of nickel 50 o C Cathode-to-anode current density ~ 2.5 ma/cm 2 Electroplated Nickel Electroplated Nickel Strip the PR in PRS2000 Remove the Ni seed layer in Ni wet etchant Release the structures Use a K 4 Fe(CN) 6 /NaOH etchant that attacks Al while leaving Ni and Au intact Etch selectivity > 100:1 for Al:Ni and Al:Au EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 39 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 40 Nickel Surface-Micromachining Example Below: Surface-micromachined in nickel using the described process flow 3D Pop-up MEMS EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 41 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
5 Pop-Up MEMS First MEMS hinge [K. Pister, et al., 1992] Pop-Up MEMS Pictured: hinged Campanile made in SUMMiT process, assembled using probes [Elliot Hui, et al.] Corner Cube Reflector [v. Hsu, 1999] EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 43 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/ D Direct-Assembled Tunable L Hinge Process Flow [Ming Wu, UCLA] EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 45 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
6 MUMPS: MultiUser MEMS ProcesS Foundry MEMS: The MUMPS Process Originally created by the Microelectronics Center of North Carolina (MCNC) now owned by MEMSCAP in France Three-level polysilicon surface micromachining process for prototyping and foundry services Designed to service as many users as possible; basically an attempt to provide a universal MEMS process 8 photomasks $4,900 for 1 cm 2 dies Micromotor fabricated via MUMPS EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 47 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 48 MUMPS: MultiUser MEMS ProcesS Micromotor Example Minimum set set of of masks that must be be used in in MUMPS Masks in polymumps EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 49 Extra masks for for more Field type: flexibility & ease of of release Light (or clear) field (cf): in layout, boxes represent features that will stay through fabrication Dark field (df): in layout, boxes represent holes to be cut out EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
7 MUMPS Process Flow MUMPS Process Flow (cont.) Deposit PSG on the starting n- type (100) wafers Anneal to heavily dope the wafers Remove the PSG LPCVD 600 nm of low stress nitride LPCVD 500 nm of polysilicon Lithography using the POLY0(cf) mask and RIE etching to pattern the poly0 ground plane layer LPCVD 2 μm of PSG as the 1 st sacrificial layer Lithography using the DIMPLE(df) mask (align to poly0) RIE 750 nm deep to form dimple vias Lithography using the ANCHOR1 (df) mask (align to poly0) RIE anchor vias down to the nitride surface EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 51 LPCVD 2 μm undoped polysilicon LPCVD 200 nm of PSG Anneal for o C This both dopes the polysilicon and reduces its residual stress Lithography using the POLY1(cf) mask to define structures (align to anchor1) RIE the PSG to create a hard mask first, then RIE the polysilicon LPCVD 750 nm of PSG Lithography using the P1_P2_VIA (df) mask to define contacts to the poly1 layer (align to poly1) EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 52 MUMPS Process Flow (cont.) MUMPS Process Flow (cont.) Recoat with photoresist and do lithography using the ANCHOR2(df) mask to define openings where poly2 contacts nitride or poly0 (align to poly0) RIE the PSG at ANCHOR2 openings LPCVD 1.5 μm undoped polysilicon LPCVD 200 nm PSG as a hard mask and doping source Anneal for o C to dope the polysilicon and reduce residual stress Lithography using the POLY2(cf) mask (align to anchor2) RIE PSG hard mask RIE poly2 film Remove PR and hard mask EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 53 Poly1 Rotor Poly1 Stator Final Structure: Micromotor Lithography using the METAL (df) mask (align to poly2) Evaporate titanium (Ti) (as an adhesion layer for gold) Evaporate gold (Au) Liftoff to remove PR and define metal interconnects Coat wafers with protective PR Dice wafers Ship to customer Customer releases structures by dipping and agitating dies in a 48.8 wt. % HF solution or via vapor phase HF Anti-stiction dry, if needed EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
8 MUMPS: MultiUser MEMS ProcesS Originally created by the Microelectronics Center of North Carolina (MCNC) now owned by MEMSCAP in France Three-level polysilicon surface micromachining process for prototyping and foundry services Designed to service as many users as possible; basically an attempt to provide a universal MEMS process 8 photomasks $4,900 for 1 cm 2 dies Micromotor fabricated via MUMPS EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 55 polymumps Minimum Feature Constraints Minimum feature size Determined by MUMPS photolithographic resolution and alignment precision Violations result in missing (unanchored), under/oversized, or fused features Use minimum feature only when absolutely necessary Nominal [μm] Min Feature [μm] Min Spacing [μm] POLY0, POLY1, POLY POLY1_POLY2_VIA ANCHOR1, ANCHOR DIMPLE METAL HOLE1, HOLE HOLEM EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 56 MUMPS Design Rules (cont.) MUMPS Design Rules (cont.) Oxide1 Poly1 Poly0 G N H O K R Cross Sections Cross Sections Oxide1 Poly0 POLY0 POLY0 Mask Levels Mask Levels POLY1 ANCHOR1 ANCHOR1 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 57 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
9 MUMPS Design Rules (cont.) MUMPS Design Rules (cont.) EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 59 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 60 Sandia s SUMMiT V The Sandia SUMMIT Process SUMMiT V: Sandia Ultra-planar Multi-level MEMS Technology 5 fabrication process Five-layer polysilicon surface micromachining process One electrical interconnect layer & 4 mechanical layers Uses chemical mechanical polishing (CMP) to maintain planarity as more structural layers are realized 14 masks EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 61 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
10 SUMMiT V Layer Stack Chemical Mechanical Polishing (CMP) Used to planarize the top surface of a semiconductor wafer or other substrate Uses an abrasive and corrosive chemical slurry (i.e., a colloid) in conjunction with a polishing pad Wafer and pad are pressed together Polishing head is rotated with different axes of rotation (i.e., non-concentric) to randomize the polishing Top View Carrier/Chuck DI Water Side View Slurry Pad Conditioner Slurry Platen Uses chemical mechanical polishing (CMP) to maintain planarity as more structural layers are realized Carrier Chuck Pad Pad Conditioner Wafer Backing-Film Pad EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 63 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 64 CMP: Not the Same as Lapping Actual SUMMiT Cross-Section Lapping Lapping is merely the removal of material to flatten a surface without selectivity Everything is removed at approximately the same rate Chemical Mechanical Polishing CMP is selective to certain films, and not selective to others Lapping Removes diff. materials at at same rate CMP Stops at at nonselective layer No CMP until after the first three polysi layers 1 μm mmpoly1 and 1.5 μm mmpoly2 can be combined to form a 2.5 μm polysilicon film Refer to the SUMMiT V manual (one of your handouts) for more detailed information on masks and layout instructions EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 65 EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/
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