Silicon Dioxide Layer Key to High Efficiency Crystalline Solar Cells

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1 11760 Sorrento Valley Road, Suite E San Diego, CA / fax Silicon Dioxide Layer Key to High Efficiency Crystalline Solar Cells Wet Thermal Oxide Films enable higher furnace throughput and use lower cost polysilicon Abstract: High efficiency crystalline solar cells must improve performance while replacing higher cost monocrystalline silicon with lower cost multicrystalline silicon. This is being achieved through new cell device structures that improve light trapping and energy conversion capability. These new structures depend on passivated thick and thin layers of silicon dioxide grown via wet and dry thermal oxidation. By replacing dry oxidation with wet oxidation process temperatures can be lowered from 1050ºC to 850ºC to reduce both cycle time and wafer damage. Wet oxide films can be grown at lower temperatures, which allows the use of less expensive multicrystalline substrates that degrade at higher temperatures. Wet oxide films were found to be comparable in electrical performance to dry oxide films grown after forming gas anneal. Key words: multicrystalline photovoltaic, wet thermal oxidation, PERC To reach grid parity crystalline solar cells must continue to improve efficiency and reduce cost. This can be accomplished through the use of thinner wafers and the replacement of single crystal silicon with poly-silicon or multicrystalline silicon (mc-si). Next generation high efficiency cell designs add passivation layers grown through thermal oxidation of silicon. Thermal management during growth minimizes the film defect rate and maximizes the structural integrity of the wafer. In addition, recipe pre and post oxidation process steps insure that oxide layers have been passivated and prevent or remove defects in the device generated during growth. This paper discusses the replacement of crystalline silicon with thinner wafers made from mc-si. It provides a brief overview of next generation cell design with a focus on PERC Passivated Emitter and Rear Cell construction. It discusses in detail the growth and performance of passivated wet thermal oxide films. Both theory and field results are included. High Efficiency Silicon Solar Cell Design Requirements High efficiency crystalline solar cells require three basic elements The silicon substrate must be high quality with a long carrier lifetime. 2. The cell should have low surface reflection with a good light trapping capability. 3. Emitter design should be able to collect all light generated carriers and good metal contacts for low series resistance. Multiple advanced crystalline cell types have been developed to integrate the three basic cell design requirements. These include: PERT Passivated Emitter Rear Totally diffused, PERL Passivated Emitter Rear Locally diffused, and PERC Passivated Emitter and Rear Cell. All these cells are more efficient than standard crystalline cell structures. These cell designs can be used with N and P type mc-si with adjustments to cell structure details RASIRC Page 1 of 9

2 High Quality Silicon Substrates The silicon substrate is the single most costly component in the solar cell. Reducing wafer thickness drives down cost as does the replacement of monocrystalline silicon with lower cost poly-silicon or mc-si, which is made from a less energy intensive process. However, this cost efficiency comes with a price. Reducing wafer thickness risks lower strength, difficulties in handling, thermal breakage and lower light trapping capability. Mc-Si has higher metals contamination and material variability, generally poorer electrical performance, poorer structural integrity, and lower thermal stability. Figure 1: Multicrystalline Si-Wafer 12.5 x 12.5 cm². Thickness 70 μm 2 To improve the quality of mc-si, crystal defects need to be repaired. This can be addressed through phosphorous gettering. Multicrystalline silicon usually contains high concentrations of impurities whose recombination activity limits the minority carrier lifetime, the key parameter for the efficiency of crystalline silicon solar cells. One reason for the lifetime limitation is the quantity of grain boundaries and small grain size generated during the crystallization process. In mc-si, the majority of metals are contained in precipitates at grain boundaries. These defects are hosts for recombination sites. To improve the material quality and remove impurities from the wafer, phosphorus is doped in a diffusion furnace. During high temperature phosphorous doping, metal solubility increases. Metals dissolve out of grain boundaries into the local crystal structure. Metals in the bulk move to doped regions. Depending on the temperature profile during doping, the contaminants can be removed into the doped area, locked in the bulk or clusters at grain boundaries. Higher temperatures, longer diffusion times at high temperatures and rapid cooling all lead to higher defects in the silicon since metals and point defects are locked within the structure. To prevent this, process recipes should keep temperatures as low as practical. In addition thermal ramp down should be slow to allow metals in the bulk to return to clusters at grain dislocations. Use of lower temperature and longer diffusion times have been shown to significantly improve carrier lifetime from 40 to 130 µs RASIRC Page 2 of 9

3 Another issue is that mc-si has numerous micro cracks along grain boundaries that are absent in monocrystalline silicon. As the wafers are thinned, the critical crack length diminishes. High temperature processing produces tensile stresses that expand these cracks, leading to breakage. Reduced thermal budgets for mc-si wafers will result in better carrier lifetimes and improved structural integrity. Process temperature should be kept below 900ºC. Light Trapping Silicon captures light with each pass through the bulk. As the industry moves to thinner substrates, capture efficiency drops. To overcome this, the structure is modified to generate a longer internal light path and to prevent the incident light from exiting the cell. A textured front surface with an AntiReflective Coating (ARC) and SiO2 passivation layer has good light capture properties to allow the light to enter the cell. The rear surface mirror reflects internal light back into the cell substrate. The texture on the front bounces internally reflected light back into the cell. In addition some cell designs will relocate the front contact to further enhance the light collection area. Figure 2: Light Trapping Effect 1 In the rear reflector, a thick silicon oxide layer covers the entire backside except in contact areas. Reflection is 85% to 100% depending on the angle of incidence and thickness of SiO 2. For light with an incident angle larger than a critical angle of 24.4º at the Si-SiO 2 interface, the light is internally reflected. Light rays are lost when absorbed at the interface or retransmitted out of the cell. There is little absorption at long wavelengths because the absorption coefficient of SiO 2 and ARC are negligible and the textured front structure and small critical angle, makes escape difficult from the front side. At the rear, there is low absorption due to high reflectivity and thickness of SiO 2. The 2008 RASIRC Page 3 of 9

4 thicker the SiO 2 layer in the rear reflector the longer the wavelength retained. To keep the SiO 2 reflective, metal alloying from electrodes must be minimized. Sunpower has reported commercial cell designs with better than 99% light retention. 4 Emitter Design Once light has been converted to electricity is it critical to get it out of the cell. Proper emitter design collects all the light generated carriers while good metal to silicon contact minimizes series resistance to maximize current and voltage out of the cell. The PERC cell was originally developed at the University New South Wales. Further development at the Fraunhofer ISE, has resulted in cells with 21.6% efficiency. These cells use a Laser Fired Rear Contact (LFC) where a laser is used to fire the rear point contacts through the silicon oxide layer for low resistance metal contacts. These advantages include the ability to use SiO2 thick oxide on the rear surface, no required masking, very high speed process, and insensitivity to substrate resistivity and type. Figure 3: PERC High Efficiency Silicon Cell 1 To review the complete cell process, the process starts with strong phosphorus diffusion as a gettering step. Then the diffused layers are wet-chemically etched away and the front was plasma-textured. During a wet oxidation about 130 nm of silicon oxide is grown. This oxide is removed on the front side and serves as a masking layer on the rear for the phosphorus diffusion for emitter formation. After diffusion of the phosphorus, silicate glass is etched away and the thick oxide on the rear remains for rear surface passivation. A short dry oxidation passivates the front emitter. Evaporation of the front grid is followed by full area deposition of aluminum on the rear. Next is laser-firing of the contacts on the rear and Ag-electroplating of the front contact grid before the deposition of a double-layer antireflection-coating. Finally the cells are annealed in order to achieve full surface passivation and contact formation RASIRC Page 4 of 9

5 Table 1: Parameters of textured solar cells under standard testing conditions Voc [mv] jsc [ma/cm 2 ] FF [%] η [%] thick thermal oxide 663 (654) 39.4 (38.8) 80.6 (80.4) 21.1 (20.4) thin oxide / SiNx/PECVDSiOx 651 (644) 38.7 (38.2) 79.7 (77.9) 20.1 (19.1) thin oxide/h 2 -passivation/pecvd- SoOx 657 (648) 38.8 (38.4) 80.4 (78.1) 20.5 (19.4) thin oxide/pecvd-siox 654 (645) 38.9 (38.2) 77.4 (77.5) 19.7 (19.1) Table 1: The size of the cells is 4cm 2, the material used was 1 cm FZ. Values are given for the best cell and for the average of 21 cells (in parentheses). The table above compares thick silicon oxide against silicon nitride and thin silicon oxide. The thick oxide film generated efficiencies greater than 21%. 6 The table shows that highest efficiency was generated through the use of only thick oxide. All other combinations produced between 0.6% and 1.5% lower performance. Oxidation of mc-si High efficiency PERC cells include front and rear silicon oxidation layers. While the addition of oxide layers can improve light trapping and contact resistance, oxides can also show reduced electrical performance and carrier lifetimes due to thermal oxidation of the wafer. 7,8 Table 2: Oxide Thickness Over Time Thickness (ηm) 850º C 1050º C mc-si 100 C-Si mc-si 100 C-Si Dry Oxide Wet Oxide Oxides can be grown in oxygen (dry) or in water vapor (wet). The dry process is much slower than the wet oxide process which is shown in the chart above. To grow a 100nm film with 2008 RASIRC Page 5 of 9

6 oxygen will take almost 22 hours while with steam this will take less than one hour. For thin oxide like 10 nm, process time can be reduced from 1.65 hours to 7 minutes. When working with monocrystalline silicon the main disadvantage of using dry oxidation over wet is the time spent processing the wafer. However when working with thinner mc-si wafers, not only is the process time longer, but the integrity of the wafer is also degraded. During high temperature oxidation of mc-si, metals in precipitates dissolve into the bulk. Higher temperatures increase the rate of dissolution while lower oxidation temperatures and short cycle times can reduce the injection of metal contaminants. Schultz showed that reducing oxidation from 1050ºC at one hour to 800ºC at 4 hours reduced lifetime degradation from 65% to 5% for mc-si. 9 Lifetime degradation after oxidation is not always due to metals migration. Other effects can lead to lower lifetime measurements. During oxidation, the Si-SiO 2 interface becomes disordered. Many factors affect how the film will generate and what is will look like at completion. The initial surface condition is important. If the surface is not atomically flat the oxide will not grow uniformly. Thus surface texturing microstructure can play an important role in the oxide film performance. Residual surface contaminants from cleaning and handling can change the local rate of oxidation on the wafer surface. Most contaminants can be removed by reaction with oxygen during the temperature ramp up. However, if oxygen is not present the contaminants will not be volatized and will generate localized film defects. In addition to surface contaminants, a native oxide will frequently form on the wafer surface after cleaning. In a hot furnace, this porous oxide layer, SiO x,, can volatize and leave the surface increasing roughness. Si atoms can also be injected into the thin oxide layer from the interface. All of these conditions can lead to haze, pitting, and very poor electrical characteristics. Once at temperature, the oxygen can be replaced by water vapor as the source for oxidation. The growth rate of oxide films with water vapor is significantly faster than with dry oxygen which can enable lower thermal oxidation temperatures. However, the as grown wet oxide layers are of lower density and lower refractive index than the dry oxides. At the conclusion of the wet oxidation step, there again may be poor electrical characteristics at the Si/SiO 2 interface. Also, the oxide density may have been decreased by trapped hydroxyls. These problems are minimized by a final dry oxidation cycle to remove dangling bonds, remove hydroxyls, and allow Si trapped in the oxide to diffuse back to the interface. It was found that the final Qss value from all oxidations is that of the final oxidation step. 10 When the bulk of the oxidation has been completed either an oxygen or an inert gas anneal has been found to decrease the surface state charge concentration. To decrease the density of interface traps, low temperature hydrogen (or forming gas) anneal is used. Methods A wide range of lifetimes after solar cell oxidation have been reported. The post processing technique can be critical to generating acceptable lifetime values since as grown dry oxide films are superior to wet oxide films. A comparison between wet and dry oxidation film results was conducted by the Fraunhofer Institut Solare Energiesysteme. Due to the cost and dangers associated with pyrolytic torches, a RASIRC Steamer was installed on a Tempress furnace for testing purposes. The Steamer uses de-ionized water as its steam source, thus eliminating all dependence on hydrogen and oxygen gas. Designed for 2008 RASIRC Page 6 of 9

7 semiconductor and photovoltaic applications, the Steamer creates ultra high purity steam using controlled delivery systems and steam purifiers. The RASIRC Steamer uses a non-porous hydrophilic membrane that selectively allows water vapor to pass. All other molecules are greatly restricted, so contaminants in water such as dissolved gases, ions, TOCs, particles, viruses, bacteria, pyrons, and metals can be removed in the steam phase. The RASIRC Steamer eliminates the need for a carrier gas by delivering ultrapure steam at a constant positive pressure. This enables delivery of 100% pure water vapor insuring maximum theoretical oxide growth rate is achieved. Previous data from foundries growing thick oxides indicated that the RASIRC Steamer could increase oxide growth rate, wafer and across chamber uniformity, film quality, and/or reduce operating cost when compared against all other steam technologies. 11 Preliminary Results and Discussion Results demonstrated the importance of post process annealing. Dry oxide films grown at 1050ºC had significantly better lifetimes than wet oxide films grown at 850 C. However, post process steps completely changed the results. Adding first an argon anneal, wet oxide lifetimes roughly doubled. When completing the process with a forming gas anneal, the lifetimes further improved by a factor of 5.5X. On completion of these post processing steps, wet oxide films grown at 850ºC were comparable to dry oxide films grown at 1050ºC. This is surprising because wet films are known to have inferior performance to dry and higher temperature processing minimizes surface state charge. Material: FZ, 1 Ohm cm Messung: cm -3 Dry Oxidation Table 3: Lifetimes of Thermal Oxides 12 Temperature [C] Layer Thickness [nm] Initial Lifetime [μs] Lifetime after FGA anneal (425C, 25 min) [μs] Wet Oxidation (argon anneal) (argon anneal) RASIRC Page 7 of 9

8 By replacing the dry oxide step with a wet oxide step, process temperature could be lowered by 200 C. Reduction in process temperatures enables the use of mc-si, minimizes metals migration within the cell and reduces thermal stresses on the wafer. Shorter process times also enable the efficiency benefits from new cell designs by reducing manufacturing cost. Higher throughput on each furnace results in fewer furnaces, smaller floor space requirements and significantly reduced energy requirements. Conclusion High efficiency P type crystalline solar cells are using SiO 2 both for front side passivation and for backside thick oxide beneath the contacts. The oxide suppresses recombination, improves the internal reflection for improved light trapping and allows for laser fired contacts to reduce contact resistance. Significant cost reductions are enabled by replacing monocrystalline with mc-si and thicker with thinner substrates since the largest material cost is the silicon substrate itself. The combination of thinner substrates and mc-si substrates requires lower process temperature recipes be used for cell manufacturing, since substrates gradually lose structural integrity as process temperatures rise over 900 C. To achieve economic viability, process times for the additional layers required by next generation crystalline cells need to be minimized. Wet oxidation can significantly reduce process times when compared to dry oxidation. Using the RASIRC Steamer, wet thermal oxide films grown at 850ºC allowed for lifetimes that were comparable to dry oxidation grown at higher temperatures. The ability to generate 100% steam maximizes throughputs and eliminates the need for high temperature torches and the associated safety risks and high cost of using hydrogen to make water. Integration of this wet oxidation technology into the fabrication of next generation crystalline solar cells will enable the continued reduction in cost per watt of energy generated. This will lead to continued market growth and higher volumes with all the associated benefits mass production brings. References 1 Jianhua Zhao, Production Technologies For High Efficiency Crystalline Silicon Solar Cells, CEEGNanjing PV-Tech Co. Ltd, China. 2 Willeke, G.P. Dutch Solar Cell R&D seminar 2007 Utrecht 3 H. Habenicht, s. Riepe, O. Xchultz, W. Warta, Out diffusion of Metal from Grain Boundaries in Multicrystalline Silicon During Thermal Processing, (lecture, 22 nd European PV Solar Energy Conference, Sept. 3, 2007 Milan, Italy). 4 McIntosh, et.al., Light Trapping in Sunpower s A-300 solar Cells, SunPower Website RASIRC Page 8 of 9

9 5 O. Schultz, S.W. Glunz, S. Riepe, G.P. Willeke, Gettering Of Multicrystalline Silicon For High- Efficiency Solar Cells", (lecture, 22 nd European PV Solar Energy Conference, Sept. 3, 2007 Milan, Italy). 6 Schultz et.al., Silicon Oxide/ Silicon Nitride Stack System for 20% Efficient Silicon Solar Cells, (lecture, 31 st IEEE PVSC Orlando, Fl, 2005). 7 D. Groetschel1, J. Junge, M. Kaes, A. Zuschlag, G. Hahn, Plasma Texturing And Its Influence On Surface Passivation, (lecture, 23rd European PV Solar Energy Conference, Sept Valencia, Spain). 8 Lemke, et.al., Thermal Oxidation and Wet Chemical Cleaning 22 nd European PV Solar Energy Conference, Sept. 3, 2007 Milan, Italy. 9 O.Shultz et.al., 19 th European PV Solar Energy, Paris, France, June 7, Ciantar, et. al., Influence of FN Electron Injections in Dry and Dry/Wet/Dry Gate Oxides; Relation with Failure. J. Non-Cryst. Solids, 187, 144 (1995). 11 Jeffrey Spiegelman, Improved Oxide Growth Rate and Uniformity through New Steam Delivery Method White Paper, Fraunhofer communication Jan Benick August 1, RASIRC Page 9 of 9