MC74HC4094A. 8-Bit Shift and Store Register. High Performance Silicon Gate CMOS

Transcription

1 8-Bit Shift and Store Register High Performance Silicon Gate CMOS The MC74HC4094A is a high speed CMOS 8 bit serial shift and storage register. This device consists of an 8 bit shift register and latch with 3 state output buffers. ata is shifted on positive clock () transitions. The data in the shift register is transferred to the storage register when the Strobe (STR) input is high. The output buffers are enabled when the Output Enable (OE) input is set high. Two serial outputs (QS, QS 2 ) are available for cascading multiple devices. Features Wide Operating Voltage Range: 2.0 to 6.0 V Low Power issipation: I CC = < 0 A In Compliance with the Requirements efined by JEEC Standard No. 7A NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable These are Pb Free evices Typical Applications Serial to Parallel Conversion Remote Control Storage Register 6 6 SOIC 6 SUFFIX CASE 75B TSSOP 6 T SUFFIX CASE 948F 6 MARKING IAGRAMS A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G, = Pb Free Package HC4094AG AWLYWW 6 HC 4094A ALYW (Note: Microdot may be in either location) ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 0 of this data sheet. Semiconductor Components Industries, LLC, 205 February, 205 Rev. 2 Publication Order Number: MC74HC4094A/

2 STR QP 0 QP QP 2 QP V CC OE QP 4 QP 5 QP 6 QP 7 QS STR QS QS2 QP0 QP QP2 QP3 QP C2 EN3 SRG8 C/ GN 8 9 QS QP5 3 3 Figure. Pin Assignment QP6 QP7 2 2 OE Figure 2. Logic Symbol Figure 3. IEC Logic Symbol Stage Shift Register QS2 0 QS 9 STR 8 Bit Storage Register 5 OE 3 Stage Outputs QP0 QP QP2 QP3 QP4 QP5 QP6 QP Figure 4. Functional iagram 2

3 STAGE 0 STAGES TO 6 STAGE 7 Q Q Q QS FF0 FF7 Q latch QS2 Q Q STR latch latch OE QP0 QP QP2 QP3 QP4 QP5 QP6 Figure 5. Logic iagram QP7 3

4 MAXIMUM RATINGS Symbol Parameter Value Unit V CC C Supply Voltage (Referenced to GN) 0.5 to V V in C Input Voltage (Referenced to GN) 0.5 to V CC V V out C Output Voltage (Referenced to GN) 0.5 to V CC V I in C Input Current, per Pin ± 20 ma I out C Output Current, per Pin ± 35 ma I CC C Supply Current, V CC and GN Pins ± 75 ma P Power issipation in Still Air, SOIC Package TSSOP Package T stg Storage Temperature 65 to + 50 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. erating SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C mw This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GN (V in or V out ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or V CC ). Unused outputs must be left open. RECOMMENE OPERATING CONITIONS Symbol Parameter Min Max Unit V CC C Supply Voltage (Referenced to GN) V V in, V out C Input Voltage, Output Voltage (Referenced to GN) 0 V CC V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time V CC = 2.0 V (Figure ) V CC = 4.5 V V CC = 6.0 V ns 4

5 FUNCTIONAL TABLE INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS OE STR QP0 QPn QS QS2 L X X Z Z Q 6 NC L X X Z Z NC QP7 H L X NC NC Q 6 NC H H L L QPn Q 6 NC H H H H QPn Q 6 NC H H H NC NC NC QP7 Notes. H = HIGH voltage level L = LOW voltage level X = don t care Z = high impedance OFF state NC = no change = LOW to HIGH transition = HIGH to LOW transition Q 6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge CLOCK INPUT ATA INPUT STROBE INPUT STR OUTPUT ENABLE INPUT OE INTERNAL Q 0 FF0 OUTPUT QP0 Z state INTERNAL Q 6 FF6 OUTPUT QP6 Z state SERIAL OUTPUT QS SERIAL OUTPUT QS2 Figure 6. Timing iagram 5

6 C CHARACTERISTICS Symbol Parameter Test Conditions V CC (V) V IH V IL V OH V OL I IN Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Input Leakage Current V OUT = 0. V or V CC 0. V I OUT 20 A V OUT = 0. V or V CC 0. V I OUT 20 A V IN = V IH or V IL I OUT 20 A Guaranteed Limits 55 C to 25 C 85 C 25 C Unit V V V V IN = V IH or V IL, I OUT = 2.4 ma V IN = V IH or V IL, I OUT = 4 ma V IN = V IH or V IL, I OUT = 5.2 ma V IN = V IH or V IL, I OUT 20 A V V IN = V IH or V IL, I OUT = 2.4 ma V IN = V IH or V IL, I OUT = 4 ma V IN = V IH or V IL, I OUT = 5.2 ma V IN = V CC or GN 6.0 ±0. ± ± A I OZ Maximum Tri State Output Leakage Current V IN = V CC or GN V OUT = V CC or GN 6.0 ±0.5 ±5 ±0 A I CC Maximum Quiescent Supply Current V IN = V CC or GN A 6

7 AC CHARACTERISTICS (t f = t r = 6 ns, C L = 50 pf) Symbol Parameter Test Conditions V CC (V) t PHL, t PLH t PHL, t PLH t PHL, t PLH t PHL, t PLH t PZH, t PZL t PHZ, t PLZ Guaranteed Limits 55 C to 25 C 85 C 25 C Maximum Propagation elay Figure ns to QS Maximum Propagation elay Figure ns to QS Maximum Propagation elay Figure ns to QP n Maximum Propagation elay Figure ns STR to QP n Maximum 3 State Output Enable Time Figure ns OE to QP n Maximum 3 State Output Enable Time Figure ns OE to QP n t THL, t TLH Maximum Output Transition Time Figure ns t W t W t SU Minimum Clock Pulse Width High or Low Minimum Strobe Pulse Width High Minimum Set up Time to Figure ns Figure ns Figure ns Unit 7

8 AC CHARACTERISTICS (t f = t r = 6 ns, C L = 50 pf) Symbol t SU t h t h Parameter Minimum Set up Time to STR Minimum Hold Time to Minimum Hold Time to STR Test Conditions V CC (V) 55 C to 25 C Guaranteed Limits 85 C 25 C Unit Figure ns Figure ns Figure ns f MAX Minimum Clock Pulse Frequency Figure MHz C in Maximum Input Capacitance pf C out Maximum Output Capacitance pf C P Power issipation Capacitance (Note 2) pf 2. C P is defined as the value of the IC s equivalent capacitance from which the operating current can be calculated from: I CC (operating) C P x V CC x f IN x N SW where N SW = total number of outputs switching and f IN = switching frequency. 8

9 AC WAVEFORMS /f MAX Input Input t w t PLH t PHL t su t h QPn, QS Output STR Input t TLH t PLH t THL t PHL t PLH t W t PHL QS2 Output QPn Output t TLH t THL Figure 7. Waveforms showing the clock () to output (QPn, QS, QS2) propagation delays, the clock pulse width and the maximum clock frequency. Figure 8. Waveforms showing the strobe (STR) to output (QPn) propagation delays, the strobe pulse width, the clock set up and hold times for the strobe input. t f t r OE Input QPn Output: Low to Off Off to Low QPn Output: High to Off Off to High 90% 0% t PLZ t PHZ Outputs Enabled 0% 90% t PZL t PZH Outputs isabled Outputs Enabled Input Input QPn, QS, QS2 Output t su ÉÉÉ ÉÉÉ ÉÉÉ t su t ÉÉÉÉÉ h t ÉÉÉ h ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉ The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 9. Waveforms showing the 3 state enable and disable times for input OE. Figure 0. Waveforms showing the data set up and hold times for the data input. 9

10 TEST CIRCUITS TEST POINT TEST POINT EVICE UNER TEST OUTPUT C L * EVICE UNER TEST OUTPUT k C L * CONNECT TO V CC WHEN TESTING t PLZ AN t PZL. CONNECT TO GN WHEN TESTING t PHZ AN t PZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure. AC Characteristics Load Circuits ORERING INFORMATION MC74HC4094AG evice Package Shipping SOIC 6 (Pb Free) 48 Units / Rail MC74HC4094AR2G MC74HC4094ATG MC74HC4094ATR2G SOIC 6 (Pb Free) TSSOP 6 (Pb Free) TSSOP 6 (Pb Free) 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel NLVHC4094BTR2G* TSSOP 6 (Pb Free) 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable. 0

11 PACKAGE IMENSIONS 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PLANE L U PIN IENT. U S S 2X L/2 C 6X K REF 0.0 (0.004) M T U S V S A V G B U H N TSSOP 6 T SUFFIX CASE 948F ISSUE B N J J F ETAIL E ETAIL E K K ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.00) M W NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLERING FOOTPRINT* PITCH 6X X.26 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/.

12 PACKAGE IMENSIONS SOIC 6 CASE 75B 05 ISSUE K A B P 8 PL 0.25 (0.00) M B S NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS A AN B O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G.27 BSC BSC J K M P R T SEATING PLANE G 6 PL 0.25 (0.00) M T B S A S K C M R X 45 J F SOLERING FOOTPRINT* 8X X.2 6 6X PITCH 8 9 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74HC4094A/