Here I am. Modeling and Verification of Real Time and Embedded Systems. TIMES: UPPAAL: Main Goal of the tutorial

Size: px

Start display at page:

Download "Here I am. Modeling and Verification of Real Time and Embedded Systems. TIMES: UPPAAL: Main Goal of the tutorial"

Brianne Horton
7 years ago
Views:

1 Here I m Uppsl (university city) Stockholm Modeling nd Verifiction of Rel Time nd Emedded Systems A tutoril on UPPAAL Wng Yi Uppsl University, Sweden, 2005 UPPAAL: A model checker for rel time systems developed jointly y Uppsl university nd Alorg university since 199 UPPsl + AALorg = UPPAAL SWEDEN + DENMARK = SWEDEN SWEDEN + DENMARK = DENMARK TIMES: Extended version of UPPAAL, towrds tool environment for the complete system development process: from design to implementtion TIMES = Tool for Modeling nd Implemention of Emedded Systems Min Gol of the tutoril Wht is inside the tools UPPAAL TIMES Trditionl softwre development Prolem Are Anlysis REVIEWS The Wterfll Model Design Errors re detected lte or never: 0-50% of time for testing Errors detected: the lte the more expensive Implementtion Testing REVIEWS Running System

2 Introducing, Detecting nd Correcting errors Finding errors s erly s possile! HOW? A simplified version of fieled us protocol Rechle? Exmple: Fischer s Protocol 8 V Criticil Section V:=1 V=1 A1 B1 CS1 V:=2 V=2 A2 B2 CS2 Exmple: Fischer s Protocol Exmple: Petersson s lgorithm Init x=y=0 8 V Criticil Section X<100 X:=0 X>100 V:=1 V=1 A1 B1 CS1 Y<100 Y:=0 Y>100 V:=2 V=2 A2 B2 CS2 turn, flg1, flg2: shred vriles Process 1 Process 2 Loop Loop flg1:=1; turn:=2 flg2:=1; turn:=1 While (flg2 nd turn=2) wit While (flg1 nd turn=1) wit CS1 CS2 flg1:=0 flg2:=0 End loop End loop Question: no more thn one process run in CS?

3 Exmple: the Soldiers Prolem Rel time scheduling UPPAAL = UPPsl + AALorg A tool set for modelling nd verifiction of rel-time systems developed jointly y Uppsl nd Alorg University UNSAFE At At most 2 crossing t t time time Torch Need torch SAFE Mines Wht Cn Wht is Cn they is the the shortest they mke shortesttime time for for getting getting ll ll soldiers soldiers on on the the it it within sfe minutes? sfe side side? System Model A network of timed utomt Question Q (Requirement) UPPAAL No! Deugging Informtion Yes Deugging Informtion Prototypes Executle Code TIMES will do this for you! Model Checking in Nutshell MODELING How to construct Model? Modeling = progrmming+strction Progrm s Stte Mchine! Construction of Models: Concurrency Plnt Continuous sensors Controller Progrm Discrete Input ports y!?? X! Control sttes x y Output ports Model of environment (user-supplied) c c ctutors Tsk Tsk Tsk Tsk UPPAAL Model c Model of tsks (utomtic)

4 Modeling in UPPAAL: Exmple P1 P1 :: :: while True do do T1 T1 : wit(turn=1) C1 C1 : CS1; turn:=0 P2 P2 :: :: while True do do T2 T2 : wit(turn=0) C2 C2 : CS2; turn:=1 Mutul Exclusion Progrm Specifiction=Requirement, Lmport 1977 SPECIFICATION How to sk questions: Specs? Sfety Something (d) will not hppen Liveness Something (good) must hppen Relizility (Schedulility) Specifiction=Requirement, Lmport 1977 Sfety Something (d) will not hppen Liveness Something (good) must hppen Relizility (Schedulility etc) Cn we implement the specs with given resources? Specifiction: Exmples AG not (CS1 nd CS2) never CS1 nd CS2 Sfety property AG ( <=10 ) if then within 10 Bounded liveness property EF p.test Useful for deugging EF flse Generte the whole stte spce Report dedlocks etc. AG (try => AF criticl-section) (liveness)

5 Verifiction VERIFICATION Model meets Specs? Semntics of system = ll sttes + stte trnsitions (ll possile executions) Verifiction = stte spce explortion + exmintion Verifictioin = Serching Two sic verifiction lgorithms A Stte-Spce of Progrm Rechility nlysis Checking sfety properties Loop detection Checking liveness properties B : : : : (1) Is it possile to fire the oms? (2) Is it possile to go from A to B within 10 sec? Modelling in UPPAAL: exmple Verifiction: exmple P1 P1 :: :: while True do do T1 T1 : wit(turn=1) C1 C1 : CS1; turn:=0 P2 P2 :: :: while True do do T2 T2 : wit(turn=0) C2 C2 : CS2; turn:=1 T1 I2 I1 I2 T1 T2 I1 T2 I1 C2 C1 I2 T1 I2 I1 I2 T1 T2 I1 T2 Mutul Exclusion Progrm Is it possile tht P1 nd P2 rech C1 nd C2 simultneously? T1 C2 (C1 C2) is never rechle! C1 T2

6 Prolem with verifiction: Stte Explosion EXAMPLE M1 1 2 M2 10 components nd ech with10 sttes M1 x M2 1,,,, c 1, 2,,, All comintions = exponentil in no. of components 1,c 2,c,c,c Provly theoreticl intrctle # of control sttes = 10,000,000,000 =10 G Ech stte needs *(10 x 10) = 00 B Worst cse memory usge >> 000 GB Solutions Symolic Techniques: Compute Sets of Sttes insted of one-y-one Theorem provers Symolic Techniques e.g. BDD [Brynt 86] Astrction techniques [Cosot nd Cosot] Approximtion methods [Holzmn, Wng-Toi...] On-the-fly verifiction [Holzmn] Prtil order reduction [Wolper et l] Compositionl verifiction [too mny] Comining theorem provers nd model checkers Use formuls to represent sets of sttes Compute the fixed point Strt Initil set... Overlp with d sttes or Converge (fixed point)... Converge! Or fire the oms A Protocol y Philips for Audio Products -6 months for mnul proof in hours for Hytech in sec for Uppl in sec for Uppl now! Every 9 month 10 times etter performnce! End of INTRODUCTION Dec 96 Sep 98

7 OUTLINE Introduction Lecture 1: Motivtion, exmples, prolems to solve Modeling nd Veriction of Timed Systems Lecture 2: Timed utomt, nd timed utomt in UPPAAL Lecture : Symolic verifiction: the core of UPPAAL Lecture : Verifiction Options in UPPAAL nd/or Demo Towrds Unified Frmework Lecture 5: Modeling, verifiction, rel time scheduling, code synthesis From UPPAAL to TIMES

One Minute To Learn Programming: Finite Automata

One Minute To Learn Programming: Finite Automata Gret Theoreticl Ides In Computer Science Steven Rudich CS 15-251 Spring 2005 Lecture 9 Fe 8 2005 Crnegie Mellon University One Minute To Lern Progrmming: Finite Automt Let me tech you progrmming lnguge