MOSFET Small Signal Model and Analysis
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- Denis Quinn
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1 Just as we did with the BJT, we ca csider the MOSFET amplifier aalysis i tw parts: Fid the DC peratig pit The determie the amplifier utput parameters fr ery small iput sigals.
2 + V 1 - MOSFET Small Sigal Mdel ad Aalysis i 1 i + N-Liear -V relatiship (BJT, MOSFET, etc ) V - Liearize er small sigal rage + V 1 - i 1 Liear i + Tw Prt Netwrk V - i i Geeral y-parameter Netwrk 1 y 11 V 1 + y 1 V y 1 V 1 + y V MOSFET y-parameter Netwrk y 11 V + y 1 V y 1 V + y V
3 [ [ [ y 11 y 1 V [ [ [ y 1 y V y ij j V i V, Q, V, Q y 11 V + y 1 V y 1 V + y V Deriatie f curret-ltage equati ealuated at the Quiescet Pit MOSFET Amplifiers are biased it Saturati (r Actie Mde) [ ( V VTN ) ]( 1+ V ) fr V V VTN λ 1.) put Cductace.) Output Cductace 3.) Trascductace 0 0 ad 0 y 0 ad y1 V V V y y 11 1 T V λ ( V V ) ( V V )( 1+ λ V ) T 0
 fr V V VTN λ 1.) put Cductace.](/docs-images/43/21442478/images/page_3.jpg ") Output Cductace 3.")
4 Cmpare with BJT Results There is a large amut f symmetry betwee the MOSFET ad the BJT MOSFET BJT y g λ ( V V ) T 1 λ + V Each f these parameters act i the same maer y V A C + V CE y 1 g m ( V V )( 1+ λ V ) T V V TN y 1 V C T
5 Puttig the mathematical mdel it a small sigal equialet circuit Cmpare this t the BJT small sigal equialet circuit
6 Example: Jaeger Calculate the ltage gai, A / s Gie: 1 ma/v, λ0.015 V -1 Bias Pit f: ma, V 7.5V
7 Example: Jaeger g λ ( V V ) g m ( V VT )( 1+ λ V ) T g ma m 1 ma/ V V.11 ms Need t fid V -V T [ ( V V ) ]( 1+ λ V ) V [ ( V V ) ]( (7.5)) TN g TN TN µ 1.9V S r 36.9kΩ
8 Example: Jaeger A s 1Meg 10k + 1Meg A s s s s 0.99 ad 7.7 [ V / V ] g m ( r Rd R3).1mS( 3.48k) 7.35
9 Oerlap f Gate Oxide Add i capacitaces Oerlap f Gate Oxide LD Gate t chael t Bulk capacitace LD Reerse Bias Jucti capacitaces
10 Cmplete Mdel f a MOSFET Oerlap f Gate Oxide g mb g m SB γ V + φ F Due t effectie mdulati f the threshld ltage. Oerlap f Gate Oxide ad Gate t chael capacitace Gate t chael t Bulk capacitace Reerse Bias Jucti capacitaces
11 SPCE MOSFET Mdel SPCE mdels the drai curret ( ) f a -chael MOSFET usig the fllwig parameters/equatis (SPCE ariables are shw i ALL CAPPTAL LETTERS) Cutff: 0 Liear: Threshld Vltage: P W V + L 1 EFF Saturati: P W + L 1 EFF Chael Legth L EFF L-LD [ ( V VTH ) V ]( ( LAMBDA) V ) [( ) ] V VTH ( ( LAMBDA) V ) ( PH V PH ) VTH VTO + GAMMA BS
12 SPCE MOSFET Mdel Additial Parameters SPCE takes may f it s parameters frm the itegrated circuit layut desig: W ASWxL diff (surce) PSxL diff (surce)+w L diff (surce) L ADWxL diff (drai) PDxL diff (drai)+w L diff (drai) Surce Gate Drai L plysilic gate legth W plysilic gate width AD drai area AS surce area PD perimeter f drai diffusi (t icludig edge uder gate) PS perimeter f surce diffusi (t icludig edge uder gate) NRD umber f squares i drai diffusi NRS umber f squares i surce diffusi Specified i terms f the miimum feature size
13 SPCE MOSFET Mdel Additial Parameters Mst Used
14 MOSFET Amplifiers What is the Maximum Gai Pssible? AC Sigal Gate Bias s it saturated (Cstat curret)?, V but V ad V TP 0 > V TP V > V 0 fr a depleti mdemosfet s, is always satisfied. s Saturated! V TP A A A, Max, Max, Max g m λ ( V VT )( 1+ λ V ) λ ( V VT ) ( 1+ λ V ) ( V V ) T g is iteral t the trasistr ad ca t be aided. Ay additial resistr due t exteral circuitry will lwer the gai. Fr this reas curret surces are fte used as the lad istead f bias resistrs i amplifier circuits.
Transconductance. (Saturated) MOSFET Small-Signal Model. The small-signal drain current due to v gs is therefore given by
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