Operational Amplifier Circuits Comparators and Positive Feedback

Transcription

1 Operatinal Amplifier Circuits Cmparatrs and Psitive Feedback Cmparatrs: Open Lp Cnfiguratin The basic cmparatr circuit is an p-amp arranged in the pen-lp cnfiguratin as shwn n the circuit f Figure. The p-amp is characterized by an pen-lp gain A and let s assume that the utput vltage can g all the way t DD and EE. The utput vltage is given by = A ( + ) (.) Where + and crrespnd t the vltages at the nn-inverting and the inverting terminals respectively. DD EE Figure. Basic nn-inverting cmparatr. Fr the circuit n Figure, + = and =. Fr = 0, the vltage transfer characteristic versus in is as shwn n Figure. linear regin DD saturatin v δ v δ+ saturatin EE Figure. ltage transfer characteristic f nn-inverting cmparatr When > v δ +, = DD and fr < v δ, = EE. Chanitakis and Cry Spring 006 Page

2 The values v δ + and v δ is inversely prprtinal t the pen-lp gain A. vδ + vδ = DD A = EE A (.) Operatin in the linear regin is restricted t v δ < in < v δ +. Outside this range the p- amp is driven t saturatin. Fr a practical p-amp A=00000 and fr DD =0 and EE =-0, v δ + =± 50µ, a, very small vltage. There, the amplifier may be driven t saturatin very easily. Fr > 0, the vltage transfer characteristic versus in is as shwn n Figure 3. linear regin DD saturatin v δ v δ+ saturatin EE Figure 3. ltage transfer characteristic f nn-inverting cmparatr with nn-zer erence Here the characteristic is shifted t the right by. The range f in fr peratin in the linear regin is the same and the saturatin vltages are again DD and EE. Due t the large value f A, the vltage range [ v, δ v δ + ] is very small and thus fr the remainder f this treatment we will present the behavir f the cmparatr assuming infinite pen-lp gain which crrespnds t zer linear regin. There, the vltage transfer plt shwn n Figure 3 will becme as shwn n Figure 4. Here we see a transitin frm ne saturatin regin t the ther as the vltage crsses. Chanitakis and Cry Spring 006 Page

3 DD saturatin saturatin EE Figure 4. Ideal cmparatr The cmparatr may als be arranged in the inverting cnfiguratin as shwn n Figure 5 where the input signal is applied t the inverting terminal and the erence vltage is at the nn-inverting terminal. DD EE Figure 5. Inverting cmparatr Since = A ( ) the crrespnding vltage transfer characteristic is shwn n Figure 6. DD EE Figure 6 Chanitakis and Cry Spring 006 Page 3

4 Anther arrangement f an nn-inverting cmparatr and its vltage transfer characteristic is shwn n Figure 7(a). The utput vltage is again = A ( + ) (.3) The vltage, +, at the nn-inverting terminal is fund by superpsitin ant it is + = + (.4) Since = 0 the cmparatr will transitin when + crsses zer. This happens when And thus the transitin vltage is 0 = in () t + (.5) t = (.6) () + > 0 crrespnds t > () t and the utput ges psitive ( ). Similarly, + < 0 crrespnds t < () t and the utput ges negative ( ). The vltage transfer curve is shwn n Figure 7(b). p + - (t) (a) (b) Figure 7. Nn-inverting cmparatr circuit The crrespnding arrangement fr the inverting cnfiguratin is shwn n Figure 8. Chanitakis and Cry Spring 006 Page 4

5 re f p + ( t ) (a) (b) Figure 8. Inverting cmparatr and its vltage transfer characteristic. Chanitakis and Cry Spring 006 Page 5

6 A cmmn applicatin f a cmparatr circuit is in smke alarm circuits as shwn n Figure 9. cc 3 sealed regin prvides erence cc Q cc 4 smke enters this regin Q Figure 9. Smke detectr schematic cc The dides emit light which is detected by the phttransistrs Q and Q. The tp regin is sealed and thus the perating pint f transistr Q des nt change. This perating pint is used as the erence fr ur cmparatr. When smke enters the lwer regin the perating pint f phttransistr Q changes thereby resulting in a change in the vltage frm the base (n smke) value (ns). The basic vltage characteristic f the cmparatr is as shwn n Figure 0. in( ns) Figure 0 As the intensity f the light at the base f the phttransistr decreases due t smke entering the regin, the base current decreases and the vltage will increase frm the base (n smke) value (ns). When the vltage crsses the utput f the cmparatr switches frm t triggering the alarm. Chanitakis and Cry Spring 006 Page 6

7 Let s nw cnsider what happens if the time evlutin f the vltage is as shwn n Figure. in t t t t Figure Nte that as in exceeds, the vltage at the utput f the cmparatr switches frm t and the alarm is turned n. Ntice that smetime after t the vltage in begins t decrease and at time t is crsses. Nw the utput f the cmparatr switches back t and the alarm is turned ff. This fluctuatin in in might be nise in the signal r sme temprary decreases in the smke (the effect f a persn fanning at the smke detectr). The smke is still arund hwever and as it is shwn n the evlutin, the transitin vltage will be crssed numerus times turning the alarm n and ff each time. This is an undesirable peratin and we wuld like t mdify the circuit in such a way that there is sme nise immunity in the behavir f the circuit. Psitive Feedback. Schmitt Trigger Fr example, if we are able t specify a vltage range within which the state f the utput can be at either value then we shuld be able t build the apprpriate level f nise immunity. The cnceptual representatin f the idea is shwn n Figure. In this case the alarm turns n at time t and turns ff at time t aviding all the chatter in between. Chanitakis and Cry Spring 006 Page 7

8 The circuit that will accmplish this emplys psitive feedback and it is called Schmitt Trigger. The basic frm f the circuit is shwn n Figure 3. Psitive feedback is achieved by cnnecting the feedback path t the nn-inverting terminal f the p-amp. in Immunity band t t t ON OFF t OFF Figure p + Figure 3. Inverting Schmitt trigger. In ur example, the input signal is applied t the inverting terminal and cnsequently, the circuit is called Inverting Schmitt Trigger. Chanitakis and Cry Spring 006 Page 8

9 The vltage + is related t the utput vltage by the simple vltage divider frmed by resistrs and. + = (.7) Nte that + depends n the utput vltage and the in turn depends n the difference between + and : = A ( ) + The key t analyzing these psitive feedback circuits is t assume an initial cnditin. The pssible values that can take are and where >, als assume that < 0. By assuming that the initial state f is then, and the utput is + = (.8) = A H in (.9) There, as lng as < the utput will remain at H. in The transitin frm t will happen when > in H. This part f the peratin is shwn n Figure 4(a) where the vltage H. TU S when > TU, = and + =. Nw let s see what happens when starts decreasing. In rder fr a transitin t happen again the term L in has t change sign. This will happen when < L as shwn n Figure 4(b) where TL L. The cmplete vltage transfer characteristic is btained by cmbining Figure 4(a) and (b) and it is shwn n Figure 5. The vltage at which the state f the utput changes Chanitakis and Cry Spring 006 Page 9

10 depends n whether the input vltage increases r decreases. When is between TU and TL the state f can be either r - tw pssible states. Fr this reasn this circuit is als called a Bistable Multivibtatr. The vltage transfer characteristic shws that there is Hysteresis Effect. The width f the hysteresis regin, TU TL, crrespnds t the nise immunity f the trigger circuit. TU TL (a) (b) Figure 4. TL TU Figure 5. ltage characteristic f inverting Schmitt trigger Chanitakis and Cry Spring 006 Page 0

11 Nn-Inverting Schmitt Circuit When the input signal is applied t the nn-inverting terminals as in the circuit f Figure 6 the resulting circuit is the nn-inverting Schmitt trigger. p + Figure 6. Nn-inverting Schmitt trigger The vltage + at the nn-inverting terminal is a cmbinatin f the utput vltage,, and the input vltage,. + = + (.0) Since = A ( ) the transitins will ccur when + + crsses zer. 0 = + (.) T Where T represents the transitin vltage. Let s assume the initial state =. Then T = (.) And since < 0, T is psitive and we call it TU. This crrespnding part f the characteristic plt is shwn n Figure 7(a). Nw the utput is at and will stay at this state until the vltage crsses zer. This + will happen at the transitin vltage T which must satisfy This is the lwer transitin vltage given by TL 0 = + (.3) T H Chanitakis and Cry Spring 006 Page

12 TL = (.4) Fr > 0, < 0 and the crrespnding path and transitin vltage is shwn n TL Figure 7(b). The cmplete vltage characteristic is shwn n Figure 8. TU TL (a) (b) Figure 7. TL TU Figure 8 Chanitakis and Cry Spring 006 Page

13 Schmitt Trigger with eference ltage The circuit n Figure 9(a) is an inverting Schmitt trigger with a erence vltage. The analysis f the circuit prceeds as befre. The vltage + at the nn-inverting terminal is a cmbinatin f the utput vltage,, and the erence vltage,. + = + (.5) p - + TL TU S (a) (b) Figure 9. Inverting Schmitt trigger with erence vltage. (a) circuit, (b) vltage transfer characteristic By cmparing Equatin (.5) t Equatin (.8) we see that the lcatin f the transitin vltages is simply shifted by S =. In this case the transitin vltages are: TU = S + H (.6) TL = S + (.7) The vltage transfer curve f the inverting Schmitt trigger with erence vltage is shwn n Figure 9(b). Chanitakis and Cry Spring 006 Page 3

14 A nn-inverting Schmitt trigger circuit with erence vltage is shwn n Figure 0(a) with the crrespnding vltage characteristic n Figure 0(b). The transitin vltages are given by: TU = S (.8) Where TL = S (.9) S = + (.0) There, with the apprpriate chice f, and we may design a Schmitt trigger with the desired hysteresis characteristics. p - + TL TU S (a) L (b) Figure 0. Nn-Inverting Schmitt trigger with erence vltage. (a) circuit, (b) vltage transfer characteristic Chanitakis and Cry Spring 006 Page 4

15 Schmitt Trigger Oscillatr: Astable Multivibratr By cmbining negative and psitive feedback and a capacitr fr energy strage we can design a circuit that generates a square wave utput. The circuit is shwn n Figure. + - C F Figure. Astable Multivibratr Let s analyze the peratin f this circuit fr = =. Furthermre let s define the saturatin vltages and which we take t be symmetric abut zer: =. In rder t prceed we must assume an initial state fr the utput vltage. Let s start with = which gives + = (.) ecall that we are perating with the psitive feedback and thus the utput is given by = A ( + ) (.) The vltage + = is determined by the characteristics f the capacitr C and the resistr F. The frm f is the standard expnential functin f a transient C circuit. The vltage will change state (i.e. switch frm = t = ) when becmes less than. The general frm f the vltage is given by Chanitakis and Cry Spring 006 Page 5

16 )e t / F C = final + (itial final (.3) The evlutin after the first transitin ( ging frm t ) which happens when = is fund frm Equatin (.3) with itial = and final = L / F = + ( H )e t C (.4) starts t increase expnentially twards. The functin that describes the relatinship between the inputs and the utput f the p-amp is = A( ) and when crsses the utput will switch frm t and the prcess cntinuus The time evlutin f the vltages f interest are shwn n Figure where =+5, = 5 and =. Assuming that the initially = =+5 and 5 = = lts, the equatin that describes the evlutin f fr t>0 is = 3 / F H e t C (.5) t t Figure. Oscillatr vltage characteristics. Chanitakis and Cry Spring 006 Page 6

17 5 Since = 5lts, + = lts and the utput will change state nce crsses 5 lts. This happens at t = t and t satisfies 5 3 = 5 5e t / FC (.6) And slving fr t we btain t = F C ln(3) (.7) Due t the symmetry f the prblem ( = ) the time between t and t is als given H by And s the perid f the square wave is t t = T = F F C ln(3) (.8) C ln(3) (.9) An additinal cnsequence f the frequency is that the duty cycle f this square wave is 50%. If a higher (>50%) duty cycle is desired then > The general expressin fr the perid f the square wave is T = C ln + F (.30) The prf f Equatin (.30) fllws frm the analysis abve and it is left as an exercise fr the student. Nte that the perid f the square wave des nt depend n the p-amp characteristics but nly n the external cmpnents used in building the circuit. The quality f the square wave as the frequency increases is hwever dependent n the frequency characteristics f the p-amp. duty cycle = t t Chanitakis and Cry Spring 006 Page 7