L4: Sequential Building Blocks (Flip-flops, Latches and Registers) (Most) Lecture material derived from R. Katz, Contemporary Logic esign, Addison Wesley Publishing Company, Reading, MA, 993. Some material from J. Rabaey, A. Chandrakasan, B. Nikolic, igital Integrated Circuits: A esign Perspective Prentice Hall, 23. L4: 6. Spring 24 Introductory igital Systems Laboratory
Combinational Logic Review in in Combinational Circuit in in in N- in M- Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value L4: 6. Spring 24 Introductory igital Systems Laboratory 2
A Sequential System Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state Memory element Sequential circuits have memory (i.e., remember the past) The current state is held in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events L4: 6. Spring 24 Introductory igital Systems Laboratory 3
A Simple Example Adding N inputs (N- Adders) in in in2 in N- Using a sequential (serial) approach reset in Current_Sum clk L4: 6. Spring 24 Introductory igital Systems Laboratory 4
Implementing State: Bi-stability V o =V i2 V o2 =V i V i2 = V o Point C is Metastable C V o V i2 V i2 =V o V i A V o2 δ V i = V o2 V i2 = V o A Points A and B are stable (represent & ) C B V i =V o2 δ B V i = V o2 L4: 6. Spring 24 Introductory igital Systems Laboratory 5
NOR-based Set-Reset (SR) Flipflop S S R S R SR =, SR =, SR = SR = SR = SR = SR = SR = SR = R Forbidden State Reset Hold Set Reset Set SR = SR = R S?? Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) this circuit is not clocked and outputs change asynchronously with the inputs L4: 6. Spring 24 Introductory igital Systems Laboratory 6
Making a Clocked Memory Element: Positive -Latch S R G clk R and S clock sample hold sample hold A Positive -Latch: Passes input to output when is high and holds state when clock is low (i.e., ignores input ) A Latch is level-sensitive: invert clock for a negative latch L4: 6. Spring 24 Introductory igital Systems Laboratory 7 hold
Multiplexor Based Positive & Negative Latch 2: multiplexor Positive Latch Negative Latch in in out SEL Out = sel * in + sel * in "data" clk "load" clk "remember" "stored value" L4: 6. Spring 24 Introductory igital Systems Laboratory 8
74HC75 (Positive Latch) L4: 6. Spring 24 Introductory igital Systems Laboratory 9
Building an Edge-Triggered Register Negative latch M Positive latch G G Slave Master M M Master-Slave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch View pair as one basic unit master-slave flip-flop twice as much logic L4: 6. Spring 24 Introductory igital Systems Laboratory
Latches vs. Edge-Triggered Register Edge triggered device sample inputs on the event edge 7474 Transparent latches sample inputs as long as the clock is asserted Positive edge-triggered register Timing iagram: 7475 C Level-sensitive latch Bubble here for negative edge triggered register 7474 7475 Behavior the same unless input changes while the clock is high L4: 6. Spring 24 Introductory igital Systems Laboratory
Important Timing Parameters Clock Clock: Periodic Event, causes state of memory element to change Input T su T h There is is a timing "window" around the clocking event during which the input must remain stable and unchanged in in order to to be be recognized memory element can be updated on the: rising edge, falling edge, high level, low level Setup Time (T su ) Minimum time before the clocking event by which the input must be stable Hold Time (T h ) Minimum time after the clocking event during which the input must remain stable Propagation elay (T cq for an edge-triggered register and T dq for a latch) elay overhead of the memory element L4: 6. Spring 24 Introductory igital Systems Laboratory 2
74HC74 (Positive Edge-Triggered Register) 74HC74 (courtesy TI) -FF with preset and clear L4: 6. Spring 24 Introductory igital Systems Laboratory 3
The J-K J K Flip-Flop Flop J K S R J K + + J K \ Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one L4: 6. Spring 24 Introductory igital Systems Laboratory 4
J-K K Master-Slave Register Sample inputs while clock high Sample inputs while clock low J P S S K R P R 's Set Reset Catch T oggle J K Correct Toggle Operation J φ K P \ P \ Master outputs Slave outputs Is there a problem with this circuit? L4: 6. Spring 24 Introductory igital Systems Laboratory 5
Pulse Based Edge-Triggered J-K J K Register Input X φ Input φ Output X t plh Schematic Output J φ K S R JK Register Schematic J φ K JK Register Logic Symbol L4: 6. Spring 24 Introductory igital Systems Laboratory 6
Flip-Flop Flop vs. Toggle Flip-Flop Flop Flip-Flop N T T (Toggle) Flip-Flop T N N- N- L4: 6. Spring 24 Introductory igital Systems Laboratory 7
Realizing different types of memory elements Characteristic Equations : J-K: T: + = + = J + K + = T + T E.g., J=K=, then + = J=, K=, then + = J=, K=, then + = J=, K=, then + = Implementing One FF in Terms of Another J C K K J C implemented with J-K J-K implemented with L4: 6. Spring 24 Introductory igital Systems Laboratory 8
esign Procedure Excitation Tables: What are the necessary inputs to cause a particular kind of change in state? + J X X K X X T Implementing FF with a J-K FF: ) Start with K-map of + = ƒ(, ) 2) Create K-maps for J and K with same inputs (, ) 3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map E.g., = =, + = then J =, K = X X X X X + = J = K = L4: 6. Spring 24 Introductory igital Systems Laboratory 9
esign Procedure (cont.) Implementing J-K FF with a FF: ) K-Map of + = F(J, K, ) 2,3) Revised K-map using 's excitation table its the same! that is why design procedure with FF is simple! JK J K + = = J + K Resulting equation is the combinational logic input to to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF. L4: 6. Spring 24 Introductory igital Systems Laboratory 2
System Timing Parameters In Combinational Logic Register Timing Parameters T cq : worst case rising edge clock to q delay T cq, cd : contamination or minimum delay from clock to q T su : setup time T h : hold time Logic Timing Parameters T logic : worst case delay through the combinational logic network T logic,cd : contamination or minimum delay through logic network L4: 6. Spring 24 Introductory igital Systems Laboratory 2
elay in igital Circuits V in V V 5% R on t t phl t plh V out V out V out 9% C L C L 5% R on % t t f t r (a) Low-to-high (b) High-to-low R v out review v in C t p = ln (2) τ =.69 RC L4: 6. Spring 24 Introductory igital Systems Laboratory 22
System Timing (I): Minimum Period In C L T h T h IN T su T cq T su T cq FF T cq,cd T logic T cq,cd CLout T l,cd T su2 T > T cq + T logic + T su L4: 6. Spring 24 Introductory igital Systems Laboratory 23
System Timing (II): Minimum elay In Combinational Logic CLout IN FF CLout T su T h T cq,cd T h T l,cd T cq,cd + T logic,cd > T hold L4: 6. Spring 24 Introductory igital Systems Laboratory 24
Shift-Register Typical parameters for Positive edge-triggered Register Tsu 2ns Th 5ns Tsu 2ns Th 5ns Tw 25ns Tplh 25ns 3ns Tphl 4ns 25ns all measurements are made from the clocking event that is, the rising edge of the clock Shift-register IN OUT IN L4: 6. Spring 24 Introductory igital Systems Laboratory 25
Clocks are not perfect: Clock Skew In Combinational Logic CLout Wire delay δ> T > T cq + T logic + T su - δ T cq,cd + T logic,cd > T hold + δ L4: 6. Spring 24 Introductory igital Systems Laboratory 26