p-channel MOSFET Models DC drain current in the three operating regions: -I D > 0 I D = 0 A ( V SG V T ) I D = µ p C ox ( W L) [ V SG V Tp ( V SD 2) ]( 1 λ p V SD )V SD ( VSG V Tp, V SD V SG V Tp ) I D = µ p C ox ( W ( 2L) )( V SG V Tp ) 2 ( 1 λ p V SD ) ( VSG V Tp, V SD V SG V Tp ) The threshold voltage with backgate effect is given by: Numerical values: V Tp = V TOp γ p (( V SB 2φ n ) 2φ n ) µ p C ox is a measured parameter. Typical value: µ p C ox = 25 µav -2 0.1µmV 1 λ p ------------------------- L V Tp = -0.7 to -1.0 V, which should be approximately -V Tn for a well-controlled CMOS process
MOSFET Small-Signal Model Concept: find an equivalent circuit which interrelates the incremental changes in i D, v GS, v DS, etc. Since the changes are small, the small-signal equivalent circuit has linear elements only (e.g., capacitors, resistors, controlled sources) Derivation: consider for example the relationship of the increment in drain current due to an increment in gate-source voltage when the MOSFET is saturated-- with all other voltages held constant. v GS = V GS v gs, i D = I D i d -- we want to find i d = (?) v gs We have the functional dependence of the total drain current in saturation: i D = µ n C ox (W/2L) (v GS - V Tn ) 2 (1 λ n v DS ) = i D (v GS, v DS, v BS ) Do a Taylor expansion around the DC operating point (also called the quiescent point or point) defined by the DC voltages (V GS, V DS, V BS ): 2 i D 1 i D i D = I D ( v v gs ) -- ( v GS 2 2 gs ) 2 v GS If the small-signal voltage is really small, then we can neglect all everything past the linear term -- i D i D = I D ( v v gs ) = I D g m v gs GS where the partial derivative is defined as the transconductance, g m.
Transconductance The small-signal drain current due to v gs is therefore given by i d = g m v gs. D i D = I D i d v gs V GS = 3 V G S B V DS = 4 V 600 500 i d v GS = V GS v gs i D (µa) 400 300 g m = i d / v gs v GS = V GS = 3 V 200 100 1 2 3 4 5 6 V DS (V)
Another View of g m * Plot the drain current as a function of the gate-source voltage, so that the slope can be identified with the transconductance: D i D = I D i d v gs V GS = 3 V G S B V DS = 4 V 600 i D (v GS, V DS = 4 V) i D 500 400 i d g m = i d / v gs (µa) 300 200 100 1 2 3 4 5 6 v GS = V GS = 3 V v GS = V GS v gs v GS (V)
Transconductance (cont.) Evaluating the partial derivative: g m = µ n C W ox ---- ( VGS V L Tn )( 1 λ n V DS ) Note that the transconductance is a function of the operating point, through its dependence on V GS and V DS -- and also the dependence of the threshold voltage on the backgate bias V BS. In order to find a simple expression that highlights the dependence of g m on the DC drain current, we neglect the (usually) small error in writing: g m W 2I 2µ n C ox ---- D = ID = L ------------------------- V GS V Tn For typical values (W/L) = 10, I D = 100 µa, and µ n C ox = 50 µav -2 we find that g m = 320 µav -1 = 0.32 ms How do we make a circuit which expresses i d = g m v gs? Since the current is not across the controlling voltage, we need a voltage-controlled current source: gate i d drain v gs source g m v gs
Output Conductance We can also find the change in drain current due to an increment in the drainsource voltage: i D W g o = ----------- = µ v n C ox ------ ( VGS V DS 2L T ) 2 λ n λ n I D The output resistance is the inverse of the output conductance 1 1 r o = ----- = ------------ g o λ n I D The small-signal circuit model with r o added looks like: i d = g m v gs (1/r o )v ds gate drain i d v gs g m v gs ro v ds source
Backgate Transconductance We can find the small-signal drain current due to a change in the backgate bias by the same technique. The chain rule comes in handy to make use of our previous result for g m : g mb i D = ----------- = v BS i D --------- V T V T ----------- v BS g mb V T γ n γ n g m = ( g m )----------- = ( g v m ) ------------------------------------ = ------------------------------------ BS 2 2φ p V BS 2 2φ p V BS. The ratio of the front-gate transconductance g m to the backgate transconductance g mb is: g mb --------- g m 2 q ε s N a 1 q ε s N a = --------------------------------------------- = -------- ------------------------------------ = 2 C ox 2φ p V C BS ox 2( 2φ p V BS ) C b ( y =0) ------------------- C ox where C b (y=0) is the depletion capacitance at the source end of the channel -- gate source C b (0) depletion region channel bulk
MOSFET Capacitances in Saturation source, fringe electric field lines gate,, drain, n n C sb q N (v GS ) C depletion overlap L D overlap L db D region In saturation, the gate-source capacitance contains two terms, one due to the channel charge s dependence on v GS [(2/3)WLC ox ] and one due to the overlap of gate and source (WC ov, where C ov is the overlap capacitance in ff per µm of gate width) 2 C gs = -- WLC 3 ox WC ov In addition, there are depletion capacitances between the drain and bulk (C db ) and between source and bulk (C sb ). Finally, the extension of the gate over the field oxide leads to a small gate-bulk capacitance C gb.
Complete Small-Signal Model The capacitances are patched onto the small-signal circuit schematic containing g m, g mb, and r o gate C gd i d drain v gs C gs C gb g m v gs g mb v bs r o source v bs C sb C db bulk p-channel MOSFET small-signal model the source is the highest potential and is located at the top of the schematic source v sg C gs g m v sg g mb v sb r o v sb gate C gd i d drain C gb C sb bulk C db
Circuit Simulation Objectives: fabricating an IC costs $1000... $100,000 per run ---> nice to get it right the first time check results from hand-analysis (e.g. validity of assumptions) evaluate functionality, speed, accuracy,... of large circuit blocks or entire chips Simulators: SPICE: invented at UC Berkeley circa 1970-1975 commercial versions: HSPICE, PSPICE, I-SPICE,... (same core as Berkeley SPICE, but add functionality, improved user interface,...) EE 105: student version of PSPICE on PC, limited to 10 transistors other simulators for higher speed, special needs (e.g. SPLICE, RSIM) Limitations: simulation results provide no insight (e.g. how to increase speed of circuit) results sometimes wrong (errors in input, effect not modeled in SPICE) ===> always do hand-analysis first and COMPARE RESULTS
MOSFET Geometry in SPICE Statement for MOSFET... D,G,S,B are node numbers for drain, gate, source, and bulk terminals Mname D G S B MODname L= W= AD= AS= PD= PS= MODname specifies the model name, for the MOSFET NRS = N (source) NRD = N (drain) PS = 2 L diff (source) = W PD = 2 L diff (drain) = W L, L diff (source) L diff (drain) W AS = W L diff (source) AD = W L diff (drain)
MOSFET Model Statement.MODEL MODname NMOS/PMOS VTO= KP= GAMMA= PHI= LAMBDA= RD= RS= RSH= CBD= CBS=CJ= MJ= CJSW= MJSW= PB= IS= CGDO= CGSO= CGBO= TOX= LD= Parameter name (SPICE / this text) SPICE symbol Eqs. (4.93), (4.94) Analytical symbol Eqs. (4.59), (4.60) Units channel length L eff L m polysilicon gate length L L gate m lateral diffusion/ gate-source overlap LD L D m transconductance parameter KP µ n C ox A/V 2 threshold voltage / zero-bias threshold channel-length modulation parameter bulk threshold / backgate effect parameter surface potential / depletion drop in inversion VTO V TnO V LAMBDA λ n V -1 GAMMA γ n V 1/2 PHI - φ p V DC Drain Current Equations: I DS = 0 ( VGS V TH ) KP I DS = ------- ( W L 2 eff )V DS [ 2( V GS V TH ) V DS ]( 1 LAMBDA V DS ) ( 0 V DS V GS V TH ) KP I DS = ------- ( W L 2 eff )( V GS V TH ) 2 ( 1 LAMBDA V DS ) ( 0 V GS V TH V DS ) V TH = V TO GAMMA( 2 PHI 2 PHI) V BS
Capacitances SPICE includes the sidewall capacitance due to the perimeter of the source and drain junctions -- n drain (area) (perimeter) C BD ( V BD ) = CJ AD CJSW PD ------------------------------------------- ( 1 V BD PB) MJ --------------------------------------------------- ( 1 V BD PB) MJSW Gate-source and gate-bulk overlap capacitance are specified by CGDO and CGSO (units: F/m). Level 1 MOSFET model:.model MODN NMOS LEVEL=1 VTO=1 KP=50U LAMBDA=.033 GAMMA=.6 PHI=0.8 TOX=1.5E-10 CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10 MJ=0.5 PB=0.95 The Level 1 model is adequate for channel lengths longer than about 1.5 µm For sub-µm MOSFETs, BSIM = Berkeley Short-Channel IGFET Model is the industry-standard SPICE model.