CMOS COMPARATOR. 1. Comparator Design Specifications. Figure 1. Comparator Transfer Characteristics.

Transcription

1 CMOS COMARATOR. Comparator Design Specifications o OH ( in+ - in- ) OL (a) OH L H ( in+ - in- ) OL (b) OS OH L H ( in+ - in- ) OL (c) Figure. Comparator Transfer Characteristics. A comparator is a circuit that has binary output. deally its output shown in Figure (a) is defined as follows:

2 O OH OL if if inin+ inin+ > 0 < 0 This is not realizable because its gain is infinity. Figure (b) shows a realizable first order transfer characteristic of a comparator. ts output is defined as follows: O A OH OL ( - ) if ( if L if ( inin+ < ( - - in+ inin+ in- ) > - inin+ ) < H ) < L H Another nonideal characteristic of practical comparator is the present of input offset. That is the output does not change until the input difference reached the input offset os. Figure (c) shows this transfer characteristic. ts output is defined as follows: O A OH OL ( - ) - A OS if ( if inin+ L if ( < ( - - in+ inin+ in- ) > - inin+ ) < H ) < L H The input offset can be minimized or ignored by proper layout. f the input step is sufficiently small the output should not slew and the transient response will be a linear response. The settling time is the time needed for the output to reach a final value within a predetermined tolerance, when excited by a small signal. Small-signal settling time is determined by the gain bandwidth product of the amplifier, this will be shown in the opamp circuit section later. f the input step magnitude is sufficiently large, the comparator will slew by virtue of not having enough current to charge or discharge the compensating and/or load capacitances. The slew rate is determined from the slope of the output waveform during the rise or fall of the output. Slew rate is limited by the currentsourcing/sinking capability in charging the output capacitor. Settling time is important in analog signal processing. t is necessary to wait until the amplifier has settled to within a few tenths of a percent of its final value in order to avoid errors in the accuracy of processing analog signals. A longer settling time implies that the rate of processing analog signals must be reduced. n the following design, a 0m signal must be resolved using the comparator in Figure and 3. The power supply rails are DD5 and SS-5. That is, the output will swing by 0 ( from 5 to 5) when the input signal swing by 0m( from 5m to 5m). The comparator gain must be at least 0,000 (0/0m). The following specifications will be used in designing the comparator in well and well processes. DD5, SS-5, A>0000, -3<CMR<3, -4.5<o<4.5, SR0/us.. Designing the Comparator with MOS nput Drivers

3 (3) DD M3 w.u l6.6u (5) M4 w.u l6.6u M6 w59.4u l6.6u D3 (6) O D4 M D D M w5.4u w5.4u l6.6u l6.6u G SS () SS () G Rb 5 GS (9) () C SS 5uA GS M w.u l6.6u (8) CL pf + o - M8 w.u l6.6u M5 w5.4u l6.6u (4) SS Figure. The CMOS Comparator mplementation with MOS input drivers. Figure shows the comparator schematic diagram implemented with MOS input drivers.. Determine the current drive requirement of M to satisfy the SR specification, if C L pf d D C L CL (SR) (E -)(0E6) 0uA dt. Determine the size of M6 and M to satisfy the output-voltage swing requirement. DS(SAT) DS(SAT) Similarly, O(min) β DS ( - DS SS DS(SAT) 4.5 ( 5) 0.5 ) DS (0E - 6) (40E - 6)(0.5) 4 GS 0 3

4 SD6(SAT) 6 DD ( - O(max) SD6 SD6(SAT) ) 5 (4.5) 0.5 (0E - 6) (5E - 6)(0.5) Calculate the gain of the second stage. A g g (5E - 6)(0E - 6)(0.666) m6 SD6 6 ds6 + g ds SD6 ( λ + λ ) (0E - 6)( ) Calculate the gain of the first stage to satisfy the overall gain. A A A A 0000 / A Determine the first stage biasing current using the minimum allowable size of, and minimum output offset. (a) Consider M4 and M6. Using the minimum size for M4, determine the current SD4 that mirror with M6. That is, 4 SD4 SD6 (0uA).85uA (b) Consider M5 and M. Using the minimum size for M5, determine the current DS5 that mirror with M. That is, DS5 SD4 DS DS5 DS 5 /.5uA DS5 DS (0uA) 4 SD3 /.5uA 5uA (c) Select the larger of the two SD4 and adjust the size of M4 SD4 6.5E - 6 (0.666) 0E SD

5 6. Determine the size of M to satisfy the gain requirement. A g ds g m + g [A ds4 DS ( λ + λ )] DS DS ( λ + λ ) DS [(00)(.5E - 6)( )] (40E - 6)(.5E - 6) 0.5 Let be the minimum size of. Then re-calculate the gain of the first stage. A A g A ds g m + g A ds4 DS DS ( λ + λ ) (4.4)(00) 44 (40E - 6)(.5E - 6)() (.5E - 6)( ) 4.4. The minimum size of M5 () in step 5(b) can be adjusted to satisfy the negative input CMR of 3. G(min) DS5(SAT) DS5(SAT) 5 SS + G(min) -3- (-5) - ( DS5(SAT) DS5 DS5 DS5(SAT) SS (.5E - 6) (40E - 6)() 5 ) + DS DS (5E - 6) (40E - 6)(0.65) T T 0.59 Select the larger of the two, 5. o adjustment needed, since this is the value used earlier in the calculation. 8. The minimum size of M3() in step 5(a) can be adjusted to meet the positive input CMR of 3. G(max) 3 DD - ( DD SD3 - G(max) 3 SD3 - - T3 T3 + + T T ) (.5E - 6) (5E - 6)( ) 5

6 Select the larger of the two, 3. o further adjustment needed. 9. Determine the size of M8 to provide as the main current mirror for the comparator. For DS5 0.5 and DS 0.5, this voltage corresponds to the value of G8-3.5 or GS8.5. Let SD8 0uA. DS8 (0E - 6) ( - ) (40E - 6)(.5 -) 8 GS8 T 4 The external resistor Rb connected between G8 and ground must be chosen to provide the required current for M8 of 0uA. R 0 0 ( 3.5) 0E - 6 G8 b DS Select the width of each transistor. AR M M M3 M4 M5 M6 M M8 (ua) T W/L W(u) L(u) Leff(u) Finding the W, L to the nearest multiple of λ0.6. AR M M M3 M4 M5 M6 M M8 (ua) T W/L W(u) * 5.4* 59.4*.*. L(u) Leff(u) *Adjusted to satisfy the balance condition to minimize the input offset voltage, os:

7 3. Designing the Comparator with MOS nput Drivers (3) DD M8 w60u l6.6u (9) M5 w30u l6.6u SD5 M w60u l6.6u Rb5k () G - SD + () GD M w5u l6.6u M w5u l6.6u () (6) (8) CL pf + o M3 w5.4u l-6.6u GS3 (5) M4 w5.4u l-6.6u M6 w.6u l6.6u - (4) SS Figure 3. CMOS Comparator mplementation with MOS input drivers. Figure 3 shows the comparator schematic diagram implemented with MOS input dricers.. Determine the current drive requirement of M to satisfy the SR specification, if C L pf d D C L CL (SR) (E -)(0E6) 0uA dt. Determine the size of M6 and M to satisfy the output-voltage swing requirement. SD(SAT) SD(SAT) DD β ( - SD O(max) DS DS(SAT) ) SD (0E - 6) (5E - 6)(0.5) Similarly,

8 DS6(SAT) 6 O(min) ( DS6 SS DS6(SAT) 4.5 ( 5) 0.5 ) (0E - 6) (40E - 6)(0.5) 4 3. Calculate the gain of the second stage. A g g (40E - 6)(0E - 6)(4) m6 DS6 6 ds6 + g ds DS6 ( λ + λ ) (0E - 6)( ) Calculate the gain of the first stage to satisfy the overall gain. A A A A 0000 / A Determine the first stage biasing current using the minimum allowable size of, and minimum output offset. (a) Consider M4 and M6. Using the minimum size for M4, determine the current SD4 that mirror with M6. That is, DS4 SD5 DS4 4 6 DS6 (0uA) 4 (5uA) 0uA 5uA (b) Consider M5 and M. Using the minimum size for M5, determine the current DS5 that mirror with M. That is, SD5 DS4 SD SD5 SD 5 /.85 / 0.93uA SD5 SD (0uA) /.85/ 0.93uA.85uA DS3 (c) Select the larger of the two SD4 and adjust the size of M4 if necessary. The larger SD4 5uA from 5(a). o adjustment needed, since this is the value use in calculation. 6. Determine the size of M to satisfy the gain requirement. 8

9 A g ds g m + g [A ds4 SD ( λ + λ )] SD SD ( λ + λ ) SD [(00)(5E - 6)( )] (5E - 6)(5E - 6).666. The minimum size of M5 () in step 5(b) can be adjusted to satisfy the positive input CMR of 3. G(max) G(max) SD5(SAT) SD5(SAT) DD DD DD - ( - SD5(SAT) SD5(SAT) G(max) (5E - 6) (5E - 6)(.666) SD5 SD5 DS5(SAT) 5 ) - SG SD SD 0.5 (0E - 6) (5E - 6)(0.5) T T Select the larger of the two, and adjust the size of M for proper mirroring with M (5.333) The minimum size of M3 or M4() in step 5(a) can be adjusted to meet the negative input CMR of - 3. G(min) 3 SS + ( G(min) DS3 - SS 3 DS3 - + T3 T3 + T T ) (40E - 6)[-3- (5E - 6) (-5) -+ ] 6 Select the larger of the two, 3. o further adjustment needed. 9

10 9. Determine the size of M8 to provide as the main current mirror for the comparator. For SD5 0.5 and SD 0.5, this voltage corresponds to the value of G8 3.5 or SG8.5. Let SD8 0uA. SD8 (0E - 6) ( - ) (5E - 6)( ) 8 SG8 T The external resistor Rb connected between G8 and ground must be chosen to provide the required current for M8 of 0uA. R E - 6 G8 b DS Select the width of each transistor. AR M M M3 M4 M5 M6 M M8 (ua) T W/L W(u) L(u) Leff(u) Finding the W, L to the nearest multiple of λ0.6. AR M M M3 M4 M5 M6 M M8 (ua) T W/L W(u) L(u) Leff(u) *Adjusted to satisfy the balance condition to minimize the input offset voltage, os: W W W W

11 4. Comparator Simulation 4.. CMOS Comparator mplementation with MOS nput Drivers The Spice netlist is given below: * Filename"diffcmp.cir" * MOS Diff Amp with MOS nput Drivers and Current Mirror Load * nput Signals 0 DC 0 OS 0 DC 0 * ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for CMOS COMARATOR in well M 5 4 MOS W5.4U L6.6U M 6 4 MOS W5.4U L6.6U M M MOS W.U MOS W.U L6.6U L6.6U M MOS W5.4U L6.6U M M MOS W59.4U L6.6U MOS W.U L6.6U M MOS W.U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.DC -mv m u.tf (8).ROBE.ED

12 To eliminate the input offset voltage, the negative of os is applied at the negative input of the comparator. That is, the Spice entry for OS is modified as follow: OS 0 DC 39.85uv **** SMALL-SGAL CHARACTERSTCS (8)/.8E+04

13 UT RESSTACE AT.000E+0 OUTUT RESSTACE AT (8).69E Comparator Transient Response Slew Rate Measurement * Filename"diffcmp.cir" * MOS Diff Amp with MOS nput and Current Mirror Load * nput Signal 0 WL(0,-5 0us,-5 0.0us,5 30us, us,-5 s, -5) OS 0 DC u *ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for Slew Rate Measurement * etlist for CMOS COMARATOR in well M 5 4 M 6 4 MOS W5.4U MOS W5.4U L6.6U L6.6U M MOS W.U L6.6U M M MOS W.U MOS W5.4U L6.6U L6.6U M MOS W59.4U L6.6U M M MOS W.U L6.6U MOS W.U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 *Analysis.TRA.ns 40us.ROBE.ED 3

14 4..3 Comparator Transient Response Settling Time Measurement * Filename"diffcmp.cir" * MOS Diff Amp with MOS nput and Current Mirror Load * nput Signal 0 WL(0,-5m 0us,-5m 0.0us,5m 30us, 5m 30.0us,-5m s, - 5m) OS 0 DC 0 *ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for CMOS COMARATOR in well M 5 4 M 6 4 MOS W5.4U MOS W5.4U L6.6U L6.6U M MOS W.U L6.6U M M MOS W.U MOS W5.4U L6.6U L6.6U M MOS W59.4U L6.6U M M MOS W.U L6.6U MOS W.U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U 4

15 + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 *Analysis.TRA.ns 40us.ROBE.ED Upper output voltage for 5% settling time, 0.95(o(max))0.95(4.85)4.6 Lower output voltage for 5% settling time, 0.95(o(min))0.95(-5) Comparator Open-loop Transfer Function * Filename"diffcmp4.cir" * MOS Diff Amp with MOS nput and Current Mirror Load * nput Signal 0 AC *ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for CMOS COMARATOR in well M 5 0 MOS W5.4U L6.6U M 6 MOS W5.4U L6.6U M MOS W.U L6.6U M M MOS W.U MOS W5.4U L6.6U L6.6U M MOS W59.4U L6.6U M MOS W.U L6.6U 5

16 M MOS W.U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 *Analysis.AC DEC 0 0.HZ 00MegHZ.ROBE.ED 4.. CMOS Comparator mplementation with MOS nput Drivers * Filename"diffcmpp.cir" * CMOS Comparator with MOS nput Drivers * nput Signals 0 DC 0 OS 0 DC 0 * ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for CMOS Comparator in well M 5 MOS W5U L6.6U 6

17 M 6 MOS W5U L6.6U M M MOS W5.4U MOS W5.4U L6.6U L6.6U M MOS W30U L6.6U M M MOS W.6U L6.6U MOS W60U L6.6U M MOS W60U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.DC -mv m u.tf (8).ROBE.ED To eliminate the input offset voltage the negative of os is applied - input. OS 0 DC 88.50u

18 **** SMALL-SGAL CHARACTERSTCS (8)/.96E+04 UT RESSTACE AT.000E+0 OUTUT RESSTACE AT (8).84E Comparator Transient Response for Slew Rate Measuremnt * Filename"diffcmpp.cir" * MOS Diff Amp with MOS nput and Current Mirror Load * nput Signal 0 WL(0,-5 0us,-5 0.0us,5 30us, us,-5 s, -5) OS 0 DC 0 *ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for CMOS Comparator in well M 5 MOS W5U L6.6U M 6 MOS W5U L6.6U M MOS W5.4U L6.6U M MOS W5.4U L6.6U M MOS W30U L6.6U M MOS W.6U L6.6U M MOS W60U L6.6U M MOS W60U L6.6U * External Components CL 8 0 pf RB

19 * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 *Analysis.TRA.ns 40us.ROBE.ED 4.. Comparator Transient Response for Settling Time Measurement * Filename"diffcmpp.cir" * MOS Diff Amp with MOS nput and Current Mirror Load * nput Signal 0 WL(0,-5m 0us,-5m 0.0us,5m 30us, 5m 30.0us,-5m s, - 5m) OS 0 DC 0 *ower Supplies DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for Slew Rate Measurement * etlist for CMOS Comparator in well M 5 M 6 MOS W5U MOS W5U L6.6U L6.6U M MOS W5.4U L6.6U M M MOS W5.4U MOS W30U L6.6U L6.6U M MOS W.6U L6.6U 9

20 M MOS W60U L6.6U M MOS W60U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 *Analysis.TRA.ns 40us.ROBE.ED 4..3 Comparator Open-loop Transfer Function * Filename"diffcmpp3.cir" * CMOS Comparator with MOS nput Drivers * nput Signals 0 AC OS 0 DC u * ower Supplies 0

21 DD 3 0 DC 5OLT SS 4 0 DC -5OLT * etlist for CMOS Comparator in well M 5 M 6 MOS W5U MOS W5U L6.6U L6.6U M MOS W5.4U L6.6U M M MOS W5.4U MOS W30U L6.6U L6.6U M MOS W.6U L6.6U M M MOS W60U MOS W60U L6.6U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.AC DEC 0 0.HZ 00MegHZ.ROBE.ED 4..4 Comparator Adjusted for 0-5 Operation

22 * Filename"diffcp5.cir" * CMOS Comparator with MOS nput Drivers * nput Signals 0 DC 0 OS 0 DC.5 * ower Supplies DD 3 0 DC 5OLT SS 4 0 DC 0OLT * etlist for CMOS Comparator in well M 5 MOS W5U L6.6U M 6 M MOS W5U MOS W5.4U L6.6U L6.6U M MOS W5.4U L6.6U M M MOS W30U L6.6U MOS W.6U L6.6U M MOS W60U L6.6U M MOS W60U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.DC.49.5 u.robe.ed

23 4..5 Comparator Transient Response for 0-5 Operation * Filename"diffcp5t.cir" * MOS Diff Amp with MOS nput and Current Mirror Load * nput Signal 0 WL(0,.495 0us, us, us, us,.495 s,.495) OS 0 DC.5 *ower Supplies DD 3 0 DC 5OLT SS 4 0 DC 0OLT * etlist for CMOS Comparator in well M 5 M 6 MOS W5U MOS W5U L6.6U L6.6U M MOS W5.4U L6.6U M M MOS W5.4U MOS W30U L6.6U L6.6U M MOS W.6U L6.6U M M MOS W60U MOS W60U L6.6U L6.6U * External Components CL 8 0 pf RB * SCE arameters.model MOS MOS TO 40U + GAMMA.0 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS MOS TO- 5U + GAMMA0.6 LAMBDA0.0 H0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW0E-0 + U000 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 *Analysis 3

24 .TRA.ns 40us.ROBE.ED 4