CMOS Differential Amplifier

Transcription

1 MOS Differential Amplifier. urrent Equations of Differential Amplifier DD D D (7 D ( E D / G G GS GS G (0 E D / ( G (a (b Fiure. General MOS Differential Amplifier: (a Schematic Diaram, (b nput Gate oltaes mplementation. Fiure (a shows the schematic diaram of a typical differential amplifier. The differential input is iven by: ( ( ( D G G GS GS D ( ( D D GS GS GS TN GS TN ( The commonmode input sinal is iven by: G G ( The input voltaes in term of D and are iven by / (4 G D G / (5 D

2 Fiure (b shows the implementation of the ate voltaes in terms of the differential and common mode voltaes. ts PSpice implementation usin voltae controlled voltae source is iven below: D 7 0 D 0 E E D 0 Two special cases of input ate sinals are of interests : pure differential and pure common mode input sinals. Pure differential input sinals mean 0, from equation (4 and (5; G G D / D / This case is of interest when studyin the differential ain of differential amplifier, see Fiure (a. Pure commonmode input sinals mean D 0, from equation (4 and (5; G G This case is of interest when studyin the commonmode ain of differential amplifier, see Fiure 5(a. Assume both transistor drivers are matched, that is: D D D (6 / (7 D D The transistor currents satisfy the followin equations: D D D (8 OD (9 D D ( / (0 D OD D ( / ( OD Substitutin Eq(0 and Eq( to Eq(7 ( / ( / ( / D OD OD

3 Normalizin by D ( OD OD ( To simplify the equation, let x D, and y OD (4 The equation reduces to: x y y Solve for y, x ( y ( y( y ( y y x y 4 x y x 4 x y x ( 4 The result is: y x x 4 x, provided (5 Substitutin for x and y, one obtains OD D D (6 4 OD D 4 D (7 4 D D 4 D (8 4

4 D D 4 D, provided D (9 4. Low Frequency Small Sinal Equivalent ircuit With Pure Differential nput Sinal ( DD M w5.8u l5.4u (5 M4 w5.8u l5.4u D / O D M D4 w9.6u M D (6 l5.4u D w9.6u G l5.4u G ( ( GS GS D / O (4 (a S S4 m ds v s4 D D4 D D m (v id / S dsds S m (v id / (b 4

5 Fiure. Differential Amplifier mplementation: (a Differential Amplifier with PMOS current mirror load, (b Small Sinal Equivalent ircuit for Purely Differential nput Sinal. An active load acts as a current source. Thus it must be biased such that their currents add up exactly to. n practice this is quite difficult. Thus a feedback circuit is required to ensure this equality. This is achieved by usin a current mirror circuit as load, as in Fiure. The current mirror consists of transistor M and M4. One transistor (M is always connected as diode and drives the other transistor (M4. Since GS GS4, if both transistors have the same, then the current D is mirrored to D4, i.e., D D4. The advantae of this confiuration is that the differential output sinal is converted to a sinle ended output sinal with no extra components required. n this circuit, the output voltae or current is taken from the drains of M and M4. The operation of this circuit is as follows. f a differential voltae, D G G, is applied between the ates, then half is applied to the atesource of M and half to the atesource of M. The result is to increase D and decrease D by equal increment,. The increase D is mirrored throuh MM4 as an increase in D4 of. As a consequence of the increase in D4 and the decrease in D, the output must sink a current of. The sum of the chanes in D and D at the common node is zero. That is, the node is at an ac round, see Fiure (b. From Eq(4 and Eq(5 for pure differential input sinal means the commonmode sinal is zero. That is, the input sinals are G D / and G D /. This is shown in Fiure (a. The transconductance of the differential amplifier is iven by: O md D D D / s m That is, the differential amplifier has the same transconductance as a sinle stae common source amplifier. 5

6 G v id / D m (v id / ds DGG4 v s ds m v s4 D m (v id / D4 v s4 ds v o S S (a S S4 G v id / S D D4 m (v id / ds S S4 (b v o G D D4 v id S m v id ds S S4 (c v o Fiure. Differential Amplifier Operatin in Purely Differential nput Sinal: (a Oriinal Equivalent ircuit, (b Reduction to Twoport Network, and (c hanin nput Port ariable to id. The derivation of the small sinal equivalent circuit is shown in Fiure. The simplification is based on the symmetry of the circuit. n Fiure (b, each transistor equivalent circuit is drawn. Fiure (a redraws the equivalent circuit in Fiure (b in a form suitable for twoport analysis. The further reduction is obtained after the twoport parameters are obtained. From Fiure (a, the followin twoport variables and load are obtained. L and 0 D O / The port current equations are derived to obtain the parameters: 0 (0 ( m s4 ( ds 6

7 m ( s4 ds ds m Substitute eq( to eq( m ( m m ds ds ( m ds ds m ds m m ( ( ds ds ( assumin >> m m m The resultin parameter matrix is: m ds ds 0 m ds 0 The dc voltae ain is, A D0 id O / y y L m ds nstead of half differential input, dc ain with respect to full differential input is desired. That is, A DO O m m (4 id ds ds 7

8 ( DD M w5.8u l5.4u (5 M4 w5.8u l5.4u O B0uA D (6 D4 M D D M w9.6u w9.6u l5.4u l5.4u G ( ( G o GS (8 GS (9 0uA M6 w.6u l.u M5 w.6u l.u (4 Fiure 4. The omplete Differential Amplifier Schematic Diaram Fiure (c is the resultin twoport equivalent circuit. Except for the polarity this ain equation is identical to that of the sinle NMOS inverter with PMOS current load. Fiure 4 shows the complete differential amplifier implemented usin a pair of inverter amplifier with PMOS current load, and 00uA current souce. The PSpice netlist is iven below: * Filename"diffvid.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D D 7 0 D 0 A E E D 0.65 DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W.6U L.U B 9 0UA.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 8

9 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.D D TF (6 D.PROBE.END The operatin point current is determined by the source current, which is split between the two PMOS current loaded inverters. DSQ DSQ /, and similarly DSQ DSQ4 /. For the iven differential amplifier 0uA. The voltae ain is computed as follows: N P N P4 K K N P (W (W N P / L / L P N (40E 6(9.6u/(5.4u * 0.5u (5E 6(5.8u/(5.4u * 0.5u 87.uA/ 87.95uA/ m m N DSQ (87.E 6(0E umho m P DSQ (87.95E 6(0E 6 9. umho ds λ λ λ DS DS4 DS5 DSQ DSQ4 DSQ λ λ λ P N P DSQ DSQ DSQ5.0(0E 6. umho.0(0e 6. umho.0(0e umho A m 8.59E 6.E 6.E 6 D ds.5 9

10 The low frequency input resistance Rin. The output resistance Rout /( ds /(.E6.E6.7M, see Fiure (d, and the computation above. These calculations aree well with Pspice simulation results of: **** SMALLSGNAL HARATERSTS (6/D.47E0 NPUT RETANE AT D.000E0 OUTPUT RETANE AT (6.4E05. Determination of the input commonmode rane 0

11 DD s s4 SD M M4 SD4 DG G M M G GS GS o GG M5 DS5 S S4 m ds v s4 D D4 D D m v s dsds m v s o S S Fiure 5. Differential Amplifier with Purely ommonmode nput Sinal: (a Schematic Diaram, and (b Small Sinal Equivalent ircuit. The input commonmode rane is the rane of commonmode voltae ic G G in which all the transistors are operatin in saturation reion. To determine this a purely commonmode input is applied at both inputs, see Fiure 5.. Maximum G or G Determination As G approaches DD transistor M and M o into the triode reion. G (max is the value of the input when it occurs. This can be determined from Fiure 5 by writin the KL equation from DD toward G.

12 G DD DD SD SG DG DG, since D G DS SG ( GS TP TP P TP G DD DS P TP DG From Fiure 5(a, DG can be determined in term of the commonly known transistor voltaes of M. or DG DS DS GS GS DG Transistor M is on saturation when the followin condition holds. GS That is, TN TN DG DS GS DG The minimum value of DG is achieved when transistor M is on the threshold of saturation. That is, TN DG The maximum input voltae is obtained when TN DG. That is, G (max DD DD DS P DS P DD TP TN P (5 Assumin TP TN.. Minimum G or G Determination

13 As G approaches, M becomes cutoff. The minimum input voltae G is determined when M5 is no loner in saturation. This is obtained by writin the KL equation from to G. G DS5 GS Transistor M5 is on saturation when, GS5 TN5 DS5 M5 is at vere of saturation when, GS5 TN5 DS5 DS5(SAT That is, the minimum input voltae occurs when,. G DS5(SAT GS GS5 TN5 DS5(SAT (min (6 (min ( G GS5 TN5 GS G (min GG GG ( GG TN5 DS N DS N GG TN5 ( TN N GS TN TN (7 norin the bulk bias effect. Usin the SPE parameters for the differential amplifier implemented in Fiure 4. From Eq(5, (max G P P DD K (W / L P (5E 6(5.8u/(5.4u *0.5u ua/ 0E 6 G (max E 6 and from Eq(7, 0E 6 G (min GG N To uarantee that the differential amplifier stays on the linear reion of operation, set commonmode sinal at half way the commonmode rane. That is, [ G (max G (min]/[0.9.8]/ Low Frequency Small Sinal Equivalent ircuit With Pure ommonmode nput Sinal

14 ic G v s D DGG4 D D4 v s v s4 m v s m v s ds v S D5 c S o ds ds m v s4 S S5 S4 (a ic G v s D DGG4 D D4 v s ds ds m m v s m v s ds S D5 c S v o S S5 S4 (b G D D ic s m v s S D5 ds ds L ds m v o S5 S Fiure 6. Small Sinal Equivalent ircuit: (a Oriinal Small Sinal Equivalent ircuit, (b Accountin for Source alues and Polarities, and (c Twoport onversions. Fiure 5(a shows the schematic when a purely commonmode input is applied at both inputs that is, G G. f increases both D and D increases. Their sum at the common node also increases. Fiure 5(b shows that is not at ac round, unlike the pure differential input sinal case shown in Fiure (b. Due to sinal symmetry when both inputs are the same, DS DS4. Since both G and S of M and M4 are connected to each other, means GS GS4. M is diode connected with G and D connected, means GS DS. From these expressions, DS4 GS4 can be deduced. That is the voltae (c 4

15 across D and S of M4 can be labelled as GS4, see Fiure 6(a. The current source of M4 is therefore reduced to conductance, see Fiure 6(b. Since DS DS4, the D and D4 can be connected toether. Fiure 6(c shows the final equivalent circuit after combinin all components that are in parallel. L and From Fiure 6(c, the followin twoport variables and load are obtained. ds assumin O ds m m ds The twoport current equations are derived to obtain the parameters. 0 ( ds m ds m ds ( ds ( m ds ( ds ds ds m m ( ( ds ds ds ds ( ds m ( ds ds m m ds m The parameter matrix is: 0 m ds ds m 0 m ds m assumin ds ds m ds ds 0 ds ( ds ds 0 m ds m The dc commonmode voltae ain is, 5

16 A 0 y y ds m ds assumin ( m L >> m m ds ds. ds ds ds m m m ds ( ds m m ( m m r m m ds m m r m m m r m * Filename"diffvic.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D 7 0 D 0 E E D 0 DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W00.8U L.6U M7 9 9 PMOS W.6U L.6U.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.OP.D TF (6.PROBE.END 6

17 A O r m (9.E 6(.7E This is very closed to the PSpice simulation result. **** SMALLSGNAL HARATERSTS 7

18 (6/.459E0 NPUT RETANE AT.000E0 OUTPUT RETANE AT (6.86E05 The oal of differential amplifier is to amplify the difference sinal and to reject commonmode sinal. A fiure of merit called commonmode rejection ration (MRR is defined as: MRR A A D Differential Gain Frequency Response 8

19 DD M s s4 M4 db db4 d4 G d GS M db db M GS d G L (a DD M M4 d db db s s4 d db db4 L d4 (5 (6 ( ( G M M (8 GS GS G (b Fiure 7. Parasitic apacitances of Differential Amplifier Operatin in Purely Differential nput Sinal: (a Parasitic apacitances of each Transistor, (b Lumped Parasitic apacitances. Fiure 7(a shows all the parasitic capacitances of the differential amplifier with purely differential input sinals. Since both inputs are voltae sources, they are at ac round when considerin the effects of ate capacitances. Fiure 7(b shows that there are basically three capacitances. These are: d d d4 db db db db4 s L s4 9

20 G v id / D DGG4 S m (v id / S ds ds m D D4 m (v id / v s4 S S4 ds v o d db db s s4 d db db4 L d4 (a G D DGG4 D D4 id / s4 O m (v id / m (v id / v s4 S S S S4 (b m m Fiure 8. Hih Frequency Small Sinal Equivalent ircuit: (a Small Sinal Equivalent ircuit Showin Lumped apacitances, (b Small Sinal Equivalent ircuit ombinin apacitance and Resistance to Admittance. NOTE is not a miller capacitance, it is connected between the outputs of the two inverter amplifiers, and not between an output and an input terminals of an amplifier. in this case is normally small and can be inored. Fiure 8(b shows that the three admittances are iven by: ds ds s ds s d4 m s s The twoport parameters are to be determined. Fiure 8(b shows that the twoport variables are: 0 L / and id O 0

21 m m m m m m s4 s4 s4 m s4 s4 s4 m s4 m s4 m s4 ( ( ( Solve for 0 ( 0 ( At node D ( ( ( 0 The parameter matrix is: m m m 0 0 For differential amplifier the assumption that or is approximately 0 is valid. That is, m m 0 0 The differential ain is iven by:

22 A D m y y ( ( ds ds m m ds ds L ds m s m m s ( ds ds m s ds ds m ( ds ds m s s ds ds m ds s s ds ds ds ( ds m ds m ( m( m ds s ds ds m m s s ( s ds ds The differential ain when the input voltae is chaned to D is: A p p D A where : z ds O id DO ds ds p << p << z s m ds s ds s ( z s s ( ( p p ds ds m m m m ds ds ds m m s ds NOTE the differential voltae ain has polezero doublets. That is, the zero z is double that of the nondominant pole p. The dominant (lowest frequency pole p occurs at the output node. The above transfer function can also be obtained by notin that each pole correspond to a node in the differential amplifier.

23 Each node is at a finite impedance with respect to round. That is, each node there is a resistance R n (or conductance and capacitance n to round. To determine which poles are dominant (or more sinificant, the impedance levels must be monitored. The parasitic capacitances n are of approximately the same manitude, but R n usually vary considerably. When the resistance (conductance is hih (low, a dominant pole is enerated. The impedance levels are summarized in the follwin table: Node(From Netlist Resistance apacitance Pole 0 (ac round X 0 (ac round X 5 R 5 /( ds ds m p /(R 5 * 6 R 6 /( ds p /(R (ac round X The derivation shows that the pole p create a zero doublet. * Filename"diffreq.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D D 7 0 D 0 A E E D 0.65 DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W00.8U L.6U M7 9 9 PMOS W.6U L.6U.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.A DE 00 HZ 00000GHZ.PROBE.END

24 6. ommonmode Frequency Response 4

25 DD M M4 G M M G sb sb GS GS o d5 GG M5 db5 DD M M4 G M M G GS GS o GG M5 S S sb sb db5 d5 Fiure 9. Differential Amplifier Operatin in Pure ommonmode nput Sinal: (a All Parasitic apacitances at ommon Node c, (b Total apacitances Across the Drain and Source of M5. From the expression of the dc commonmode ain, it is primarily a function of m and r. The first order frequency response analysis can be simplified by inorin all parasitic capacitances except the capacitance S across r, see Fiure 9. That is r is replaced by z in the the commonmode ain expression to account for frequency dependency. 5

26 z A where : S (r z sb r //S sr m sb db5 m S r sr d5 S ( sr r m S * Filename"diffreqc.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D 7 0 D 0 E E D 0.65 A DD 0 D.5OLT 4 0 D.5OLT M NMOS W9.6U L5.4U M NMOS W9.6U L5.4U M 5 5 PMOS W5.8U L5.4U M4 6 5 PMOS W5.8U L5.4U M NMOS W.6U L.U M NMOS W00.8U L.6U M7 9 9 PMOS W.6U L.6U.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.A DE 00 HZ 00000GHZ.PROBE.END 6

27 The differentialmode voltae ain decreases with increasin frequency but commonmode voltae increases. Therefore, MRR decreases with increasin frequency. 7. Desinin Differential Amplifier With Specified MR Given a commonmode rane of 0.75 < <0.75, GG, DS5 00uA, L min 5.4u, 0.5. Determine the size of each transistor in the differential amplifier circuit, see Fiure 4. GS TN. Determine the (W/L 5 to sink 00uA. DS5 W L 5 K N5 ( N GS5 ( GS5 DS5 TN5 K K (00E 6 (40E 6[ (.5 ] TN5 N W L N ( 5 GG ( GS5 DS5 08u 0 5.4u TN5 TN5. Determine (W/L (W/L from (min G (min specification From Eq(6, 7

28 GS W L (min 0.75 G W L K N DS5(SAT ( GS DS5(SAT DS 0.75 ( TN GS 0.75 (50E 6 (40E 6(.5 6u u. Determine (W/L(W/L4 from (max G (max specification From Eq(5, W L (max DS P K P ( G ( (max DD DD G DS G (max DD (max K P DS P W L ( DD G (50E 6 (5E 6( (max.75u u The above is simulated usin PSpice. The results aree well with the calculations. * Filename"diffcmr.cir" * MOS Diff Amp with urrent Mirror Load *D Transfer haracteristics vs D 7 0 D 0 E E D 0 DD 0 D.5OLT 4 0 D.5OLT M NMOS W6U L5.4U M NMOS W6U L5.4U M 5 5 PMOS W.75U L5.4U M4 6 5 PMOS W.75U L5.4U M NMOS W08U L5.4U GG 9 0 D.MODEL NMOS NMOS TO KP40U GAMMA.0 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U0550 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.MODEL PMOS PMOS TO KP5U GAMMA0.6 LAMBDA0.0 PH0.6 TOX0.05U LD0.5U J5E4 JSW0E0 U000 MJ0.5 MJSW0.5 GSO0.4E9 GDO0.4E9.D TF (6.PROBE.END 8

29 9