IEEE EDS WIMNACT-47 47 th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology MQ-1: NTU, MQ-2: NUS, MQ-3: SUTD ORGANIZED AND SPONSORED BY IEEE EDS AND R/CPMT/ED SINGAPORE CHAPTER MQ-2: CO-HOSTED BY DEPARTMENT OF ECE, NUS Date : 5 June 2015, Friday Time : 1:00pm 5:00pm Venue : E5-03-20, Faculty of Engineering (FoE), NUS Map : http://map.nus.edu.sg (Parking: Carpark 2, FoE) Admission : Free Program 1:00 1:10 Opening and Introduction to IEEE EDS 1:10 2:00 Ultra-low power and Energy Efficient Green Electronic Devices Prof. Albert Chin, National Chiao Tung University, Taiwan 2:00 2:50 Physics of High Voltage Devices and Their Applications Prof. Mitiko Miura-Mattausch, Hiroshima University, Japan 2:50 3:10 Break 3:10 4:00 Very High Voltage SiC Power Switches Energy Efficient Integrated SiC Drive Electronics Prof. Mikael Östling, KTH, Sweden 4:00 4:50 2D Nanostructure-based Future Devices Prof. Bin Yu, SUNY-Albany, USA 4:50 5:00 Closing Related websites: EDSSC2015 ECE@NUS http://www.edssc2015.org/ginfo.html http://www.ece.nus.edu.sg/
Abstracts & Speaker Biographies Ultra-low power and Energy Efficient Green Electronic Devices Prof. Albert Chin, National Chiao Tung University, Taiwan The IC chips consume a large amount of energy globally and will continue to increase. We have used high-κ technology, device design, and 3D IC to greatly lower the DC and AC power consumptions by basic phys of Q=CV & PAC=CV 2 f/2. Using La2O3 and Al2O3 high-κ dielectrics, low Vt n- and p-mosfets were achieved at 0.6~ 0.9 nm EOT. These high-κ dielectrics have been implemented in 32/28-nm CMOS manufacture. Applying high-κ dielectrics into flash memory, fast 100 μs speed, low 10 V operation, and a simple planar structure were reported by us and listed in ITRS. Such planar high-κ flash memory has also been implemented at 20 nm array manufacture. To further lower PAC, we invented the Ge-on- Insulator CMOS. Both higher hole and electron mobility were reached at 1~1.4 nm EOT for lower VD and PAC. The PAC can be further lowered by our 3D IC demonstrated by Ge CMOS. The ultimate VD and PAC reduction are limited by the slow turn-on slope (SS). We demonstrate experimentally the steep turn-on CMOS has lower IOFF and better SS for low PAC. DRAM also consumes large power and the DRAM capacitor faces scale challenge to sub-20 nm. We reported a new one-mosfet DRAM with fast switching time, long endurance, low IOFF, and large retention windows to continue DRAM scaling. Large energy saving is reachable by improving energy efficiency in power devices. The high-κ GaN MOSFET has very high ID, high VBD, small Ron for power/energy saving, normally-off, and excellent reliability. These ultra-low power & energy-efficient green electronic devices will have significant contributions to ED society. Albert Chin received Ph.D. University of Michigan. He was with AT&T Bell Labs, General Electric E-Lab and Texas Instruments SPDC. He is a pioneer on low DC-power high-κ CMOS, high-κ planar Flash memory, high mobility Ge-On-Insulator, low AC-power 3D IC, high RF power asymmetric-mosfet, Si THz devices, and resonant-cavity photo-detector. He co-authored >450 papers and 7 Highly Cited Papers. Dr. Chin served as Subcommittee Chair and Asian Arrangements Chair of IEDM Executive Committee. He is an IEEE Fellow, OSA Fellow, and Asia-Pacific Academy of Materials Academician. He serves as Editor of IEEE Electron Device Letters and IEEE EDS Technical Committee Chair on Electronic Materials.
Physics of High Voltage Devices and Their Applications Prof. Mitiko Miura-Mattausch, Hiroshima University, Japan Power devices are getting more important for renewable energy generation and distribution due to global warming. Here important tasks are to predict power consumption of systems accurately to save energy. For the purpose an accurate compact model applicable even for device optimization is prerequisite. On the other hand, the variety of power devices is huge due to very wide application ranges from a few volts to more than 10KV. According to the application, not only the device structures but also the device materials are varied nowadays. To create an accurate compact model for any applications, we have been developing the compact model HiSIM_HV based on the Poisson equation. For high accuracy, the model thus solves the potential distribution within the device iteratively, because the derivation of an analytical potential equation is possible only by introducing rigorous approximations, which restrict the model-application range. In the presentation, the origin of device features observed in power devices is reviewed with examples. The modeling approach on the basis of the Poisson equation is also explained in detail, which enables to extend the HiSIM_HV framework to many individual device types. Mitiko Miura-Mattausch: From 1981 to 1984, she was a Researcher at the Max-Planck Institute for Solid-State Physics, Stuttgart, Germany. From 1984 t0 1996, she was with the Corporate Research and Development, Siemens AG, Munich, Germany, working on hot electron problems in MOSFETs, the development of bipolar transistors, and analytical modeling of deep sub micrometer MOSFETs for circuit simulation. Since 1996, she has been a Professor at the Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima University, where she leads the Ultra Scaled Devices Laboratory. She has more than 300 publications and three books, is an IEEE fellow since 2001, and was honored by several awards.
Very High Voltage SiC Power Switches Energy Efficient Integrated SiC Drive Electronics Prof. Mikael Ostling, KTH, Sweden This presentation will give a review of present device technology status as well as discuss the most promising application areas for the high power silicon carbide device technology. A discussion of the various device concepts will be presented, including the major technologies for MOSFETs, JFETs BJTs, PN and Schottky diodes respectively. A comparison with present silicon based power device families such as IGBTs and CoolMOS will be included. Commercial and research device results will be covered. Recent results of research and demonstration of high temperature SiC devices and circuits will be presented. Mikael Östling received his MSc degree in engineering physics and the PhD degree from Uppsala University, Sweden in 1980 and 1983 respectively He has been with the faculty of EE of KTH, Royal Institute of Technology in Stockholm, Sweden since 1984 where he holds a position as professor in solid state electronics. Between 2000 and 2004 he was head of the department of Microelectronics and Information Technology. He is department head of Integrated Devices and Circuits and was the dean of the School of Information and Communication Technology, KTH, between 2004 2012. Östling was a senior visiting Fulbright Scholar 1993-94 with the Center for Integrated Systems at Stanford University, and a visiting professor with the University of Florida, Gainesville. He initiated and was appointed program director by the Swedish Foundation for Strategic Research for a silicon nanoelectronics national program 2000-2007. From 2006 he is a member of the ENIAC SCC Management Team in the EU. In 2005 he co-founded the company TranSiC. He has been frequently engaged as expert reviewer for the framework programs in EU and for the European Research Council. In 2009 he received the first ERC award for advanced investigator grant. His research interests are silicon/silicon germanium devices and process technology for very high frequency, as well as device technology for wide bandgap semiconductors with special emphasis on silicon carbide for high power applications. He has supervised 35 PhD theses work, and been the author of 1 text book, 10 book chapters and about 500 scientific papers published in international journals and conferences. Mikael Östling is an editor of the IEEE Electron Device Letters and a fellow of the IEEE.
2D Nanostructure-based Future Devices Prof. Bin Yu, SUNY-Albany, USA Discovered only eleven years ago, graphene (two-dimensional carbon atomic sheet) and its derivative material systems have received significant amount of research interests from academia and industry. These emerging 2D nanostructures exhibit unique electrical, optical, thermal, and electro-mechanical properties, attributed to their distinctive layered configuration, energy band structure, and quantum phenomena such as massless Dirac fermion transport. The atomicallythin 2D nanosheets could be potentially assembled by the existing thin-film techniques such as CVD deposition and van der Waals epitaxy, with possibility towards layer-based heterogeneous assembly. While graphene has been explored as both active and passive elements in many applications, its gap-less nature implies fundamental limitations that promote innovations in new device principle and material engineering. This talk will introduce basic structure, material preparation, and potential design and implementation of a number of nano-device prototypes on graphene and graphene-like 2D materials. Challenges and near-future research opportunities in the respective field will be also highlighted. Dr. Bin Yu received M.S. and Ph.D. degrees in Electrical Engineering from University of California at Berkeley. He is currently Professor at College of Nanoscale Science & Engineering, State University of New York. Dr. Yu s research is in the field of solid-state devices, nanoelectronics, and nanomaterials. Specific interests include energy-efficient green electronics, post-cmos devices, non-volatile memories, carbon interconnects, nanophotovoltaics, nano-sensors, and other emerging nano-devices based on 1D/2D/3D nanostructures. He has authored/co-authored 8 book/contributed book chapters, more than 250 research publications, and was the speaker of more than 100 keynote/highlight/invited talks to conferences, professional societies, universities, national labs, and industry. As one of the most prolific inventors in electronics, he has total 304 awarded U.S. patents and several dozens of European/Japanese patents, and was ranked #3 in NSF Supported Investigators with Most Patents selected nationwide in 2011. Dr. Yu served on the invited panels and advisory/technical program committees of many international conferences, and was the CMOS Subcommittee Chair of IEEE IEDM (2002-2003). He was/is Editor of IEEE Electron Devices Letters, Associated Editor of IEEE Transactions on Nanotechnology, Editor of Nano-Micro Letters, Editor of Materials Research Society Symposium, and Guest Editor of Joint Special Issue of IEEE Transactions on Electron Devices and IEEE Transactions on Nanotechnology. He is IEEE Fellow, IEEE Distinguished Lecturer, and recipient of IBM Faculty Award and NASA Innovation Award. He was appointed as Consulting Professor of Electrical Engineering at Stanford University and Guest Professor at Beijing University. Dr. Yu s prior research includes semiconductor industry s first 10-nm gate length double-gate FinFET (IEDM 2002).