Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 11 MOSFET part 2 guntzel@inf.ufsc.br
I D -V DS Characteristics of NMOS (I-V Curves) I D (A 6 x 10-4 VGS = 2.5 V 5 4 3 2 1 V DS = V GS - V T Resistive Saturation V GS = 2.0 V V GS = 1.5 V V GS = 1.0 V Quadratic dependence on V GS I D (A 2 1.5 1 0.5-4 x 10 2.5 V DS = V GS - V T V GS V DSAT = κ(v GT )V GT Velocity Saturation = 2.5 V V GS = 2.0 V V GS = 1.5 V V GS = 1.0 V Linear dependence on V GS 0 0 0.5 1 1.5 2 2.5 V DS (V) Long-channel NMOS (W/L = 1.5 and L d =10 µm) 0 0 0.5 1 1.5 2 2.5 V DS (V) Short-channel NMOS (W/L=1.5 and L d =0.25 µm) Slide 11.2
I D -V GS Characteristics of NMOS (I-V Curves) 6 x 10-4 V DS = 2.5 V (NMOS devices are saturated) 2.5 x 10-4 I D (A) 5 4 3 2 1 Subthreshold conductance 0 0 0.5 1 1.5 2 2.5 quadratic V GS (V) Long-channel NMOS (W/L = 1.5 and L d =10 µm) I D (A 2 1.5 1 0.5 Subthreshold conductance linear quadratic 0 0 0.5 1 1.5 2 2.5 V GS (V) Short-channel NMOS (W/L=1.5 and L d =0.25 µm) Slide 11.3
I D -V DS Characteristics of PMOS 0! x 10!-4! V GS = -1.0V I D (A -0.2! -0.4! -0.6! V GS = -1.5V V GS = -2.0V The polarities of all voltages and currents are reversed -0.8! V GS = -2.5V -1! -2.5! -2! -1.5! -1! -0.5! 0! V DS (V) Short-channel PMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) Slide 11.4
MOSFET NMOS x PMOS (I-V Curves) I D (A Minimum-size (short-channel) NMOS and PMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) -4 x 10 2.5 V DS = V GS - V T V GS 2 1.5 1 V DSAT = κ(v GT )V GT Velocity Saturation = 2.5 V V GS = 2.0 V V GS = 1.5 V I D (A -0.2! -0.4! -0.6! 0! x 10!-4! V GS = -1.0V V GS = -1.5V V GS = -2.0V 0.5 V GS = 1.0 V -0.8! V GS = -2.5V 0 0 0.5 1 1.5 2 2.5 V DS (V) Velocity saturation is less pronounced in PMOS (due to higher value of critical electrical field, resulting from smaller mobility of holes) Slide 11.5-1! -2.5! -2! -1.5! -1! -0.5! 0! V DS (V)
Simple Model for Manual Analysis A Single Current Source Using First-Order Expressions G S D B Employs 5 parameters, which are positive for NMOS and negative for PMOS: λ k' n V T0, V DSAT,,, γ Slide 11.6
Simple Model versus Spice Minimum-size NMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) 2.5 x 10-4 V DS =V DSAT 2 1.5 Linear Velocity Saturated I D (A) 1 0.5 V DS =V GT V DSAT =V GT 0 0 0.5 1 1.5 2 2.5 Saturated V DS (V) Slide 11.7
Parameters for Manual Analysis Minimum-size NMOS (W d =0.375 and L d =0.25 µm) V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) (V -1 ) NMOS 0.43 0.4 0.63 115 x 10-6 0.06 PMOS 0.4 0.4 1 30 x 10-6 0.1 γ λ Notice: parameters to match well in the (V DS =2.5V, V GS =2.5V) region of 0.25µm NMOS Slide 11.8
Determining the I-D Curves of PMOS Experimental setup - V GS S 1 [0,3.3] step 0,5 V + - + G 2 D 3 B I D 1 + - V DS + + - VDD = 3.3 V - [0,3.3] step 0,050 V Slide 11.9
Determining the I-D Curves of PMOS Circuit description (SPICE) PMOS1.cir http://www.inf.ufsc.br/~guntzel/ine5442/parametros SpiceOpus (c) 6 -> source PMOS1.cir SpiceOpus (c) 7 -> dc v3 0 3.3 50m v2 0 3.3 0.5 SpiceOpus (c) 8 -> plot i(v3) xlabel VD[V] ylabel ID[A] Also available NMOS1.cir Slide 11.10
Determining the I-D Curves of PMOS SpiceOpus (c) 1 -> source PMOS1.cir SpiceOpus (c) 2 -> setplot new New plot V GS =-3.3 V Current const Constant values (constants) SpiceOpus (c) 3 -> dc v3 0 3.3 50m v2 0 3 0.5 SpiceOpus (c) 4 -> plot 1000*i(v3) xlabel VD[V] ylabel ID [ma] V GS =-2.8 V V GS =-2.3 V V GS =-1.8 V V GS =-1.3 V Slide 11.11
The Transistor as a Switch ( Zero-Order Model ) Non-ideal switch Actual NMOS S V GS V T V GS R on? D What is the value of R on? Abrupt transition from on to off? & Galup, Schneider 2010 Slide 11.12
The Transistor as a Switch ( Zero-Order Model ) V DD V DS (V DD V DD /2) I D V DS > V DSAT : transistor is in velocity saturation I DSAT or with Resistance is inversely proportional to W/L Slide 11.13
The Transistor as a Switch Simulated R eq x V DD For V DD >> V T + V DSAT /2, R eq is practically independent of V DD Once V DD achieves V T, R eq increases significantly! Slide 11.14
The Transistor as a Switch R eq of NMOS and PMOS Transistors in 0.25 µm (W/L=1, L=L min ) V DD (V) 1 1.5 2 2.5 NMOS (kω) 35 19 15 13 PMOS (kω 115 55 38 31 For larger devices, divide R eq by W/L Slide 11.15
Dynamic Response of MOS Transistor Is a function of time it takes to (dis)charge: its intrinsic capacitances interconnect lines and load capacitances Origin of intrinsic capacitances: The basic MOS structure The channel charge The depletion regions of reverse-biased pn-junctions of drain and source Capacitance values depends on the applied voltages (nonlinear capacitors) Slide 11.16
MOS Gate Capacitance If: No lateral diffusion Transistor in cut-off C gate = C ox x WL where C ox = ε ox t ox Slide 11.17
MOS Structure Capacitances Top view Polysilicon gate x d x d Lateral diffusions (Area = x d x W) W Overlap capacitances (linear): C GS0 = C GD0 = = C ox x d W = C 0 W Cross section t ox L d L Gate-bulk overlap Gate oxide where C 0 = C gs0 or C gd0 = overlap capacitance per unit transistor L d = designed length; L = effective length Slide 11.18
Gate Capacitance (Piece-Wise Linear Model) Operation region Cut-off Linear Saturation C GCB C GCS C GCD C GC = C GCB +C GCS +C GCD C G Cutoff C ox WL 0 0 C ox WL C ox WL + 2C o WL Linear 0 C ox WL/2 C ox WL/2 C ox WL C ox WL + 2C o WL Saturation 0 (2/3) C ox WL 0 (2/3) C ox WL (2/3) C ox WL + 2C o WL Most important regions in digital design: saturation and cut-off Slide 11.19
Gate Capacitance C GC as a function of V GS (V DS = 0 thus, linear mode) C GC as a function of the degree of saturation V T Transistor is off (cap between gate and body) Degree of saturation Slide 11.20
Junction Capacitances (Diffusion Capacitances) Channel-stop implant N A + Side wall W Source N D Bottom x j Side wall L S Substrate N A Channel Slide 11.21
MOS Capacitances S G D Field oxide n + C GS C GD C SB C GB C DB n + p-substrate substrate (bulk) contact Slide 11.22
MOS Capacitances Consider as NMOS transistor with the following parameters: t ox = 6 nm L= 0.24 μm W= 0.36 μm L D =L S = 0.625 μm C 0 = 3 x 10-10 F/m C j0 = 2 x 10-3 f/m2 C jsw0 = 2.75 x 10-10 F/m Determine the zero-bias value of all relevant capacitances. Slide 11.23
Capacitances in a 0.25 µm CMOS Process C ox (ff/μm 2 ) CGD0 (ff/μm) CJ (ff/μm 2 ) m j Φ b (V) CJSW (ff/μm) NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9 PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9 m jsw Φ bsw (V) Slide 11.24
References MOSFET 1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3. 2. WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective. Addison-Wesley, 4 th Edition, 2010. ISBN 978-0321547743. Slide 11.25
References MOSFET 3. MURTHY, R S Ananda. A Simplified Introduction to Circuit Simulation using SPICE OPUS. September 2004. Disponível em http://fides.fe.uni-lj.si/spice/documentation.html 4. TUMA, Tadej; BURMEN, Árpád. Circuit Simulation with SPICE OPUS, Theory and Practice. Ed. Birkhäuse, 2009. ISBN 978-0-8176-4866-4 Slide 11.26