Attention. restricted to Avnet s X-Fest program and Avnet employees. Any use

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1 Attention The Content material is contained copyright in by this its presentation original authors, is the property and is used of Avnet by Electronics permission. Marketing. This compendium Use of this material is the property in it s whole of Avnet or in part is restricted to Avnet s X-Fest program and Avnet employees. Any use by Electronics non-avnet employees Marketing outside and it s of X-fest the X-Fest partners. program Use is prohibited. of this material in its whole or in part is restricted to Avnet s X-fest program, Avnet s employees, or the original copyright owner. For additional information, please contact Jim Beneke at Avnet (jim.beneke@avnet.com). For additional information or use requests, please contact Jim Beneke at Avnet (jim.beneke@avnet.com)

2 ARM Software Development for Zynq EPP Tweet this event: #avtxfest

3 Why is this course important? 3

4 Course Objectives 4 Discover the development tools available for the Zynq EPP Understand the operating system options for the dual core ARM Cortex A9 MPCore Learn how to automatically generate board support package and system documentation using tool features

5 Agenda 5 Development Tool Overview Zynq-7000 EPP Hardware Design Flow Zynq-7000 EPP Software Development Flow Choosing the Optimal Operating System Zynq-7000 EPP Boot Process Overview Closing Comments

6 Zynq-7000 EPP Architecture Overview 6 DDR Memory Hardware Designer Perspective Peripheral blocks can be standard core offerings or custom logic cores Logic controls exposed to Processor System via register interface ARM Cortex-A9 PL Peripheral 1 PL Peripheral 2 MPCore PL Peripheral 3 Fixed I/O Peripherals 256KB OCM Programmable Logic Software Developer Perspective Processor System controls Programmable Logic blocks via exposed register interface Standard address-mapped architecture similar to any other ASSP Processor Address Space DDR Memory PL Peripheral 1 PL Peripheral 2 PL Peripheral 3 Fixed I/O Peripherals 256KB OCM 0x x x x xE xFC000000

7 Zynq-7000 EPP Embedded Design Flow 7 MATLAB Simulink AutoESL HLS Software Developer System Architect Hardware Designer Xilinx ISE ARM DS-5 Xilinx SDK Programming Integrate IP Test Debug Custom IP Xilinx IP Partner IP Design Integrate IP Test Debug Xilinx XPS System Generator ELF Application Processor Bitstream Programmable Logic Zynq-7000 EPP

8 Zynq-7000 EPP Embedded Design Flow 8 Industry-Leading Tools Xilinx SDK ARM DS-5 MATLAB and Simulink System Architect Architecture Definition Hardware/Software Partitioning Processor Configuration Industry-Leading Tools AutoESL HLS System Generator MATLAB and Simulink Software Development Software Architecture Application Coding Build & Debug Firmware Development Hardware Design Boot Loader* Design & Planning Base BSP * Integrate IP* Custom Drivers & BSP Implement Verify Many Sources of Software IP Xilinx, ARM libraries 3rd Parties Simulate, Profile, & Debug Image Generation & Deployment Application Processor Programmable Logic Zynq-7000 EPP Many Sources of Hardware IP Standardized around AXI 3rd Parties

9 Hardware Design Tool Options 9 Xilinx ISE logic design support for Zynq Create Zynq Programmable Logic design(s) Add logic IP partitions to Programmable logic Team design environment for design collaboration Xilinx XPS native Zynq-7000 EPP hardware support Configure Zynq Processing System hardware settings PS peripheral selection and associated pin planning PS clock generation module DDR controller settings Connect programmable logic to Processing System AXI interfaces

10 Software Development Tool Options 10 Xilinx SDK native Zynq software support Import Zynq BSP hardware settings for target boards Create and manage Linux application projects Debug applications on target board Run Zynq benchmarking applications Profile applications Copy applications to target file system ARM Development Studio (DS-5 ) Software Tools Developed by ARM for ARM targets Industry standard Eclipse IDE Linux application and bare metal debug capability Streamline Performance Analyzer

11 System Level Development Tools 11 System level development tools for software acceleration and coprocessing applications AutoESL HLS or Embedded Coder/HDL Coder X-fest course Designing Wireless Communication Systems in Xilinx FPGAs

13 Zynq-7000 EPP Embedded Tool Flow 13 Hardware Flow ISE Programmable Logic User Programmable Logic Programmable Logic Implementation Processing System XPS PS Configuration (PS plus IP block in PL) IP Config System Wizards System Assembly Software Flow FSBL/BSP Generation SDK - Software Application Debug Application Development First Stage Boot Loader System Definition PS Register Initialization Data Programmable Logic Configuration Map of IP Location for Software

14 Xilinx Platform Studio (XPS) 14 Platform Studio is used for creation of a Zynq-7000 EPP based design Automates complex AXI connections between PS and PL Easy access to Xilinx Platform Studio soft IP catalog Embedded Wizard for custom IP creation Exports all necessary hardware information to software development environment (SDK) The ZYNQ tab is present when a Supported in IDS 14.1 Zynq-7000 EPP device is selected in the XPS project settings

15 XPS - PS Configuration 15 Used for high level configuration of the Zynq-7000 EPP PS

16 XPS - PS Peripheral and I/O Selection 16 Select Zynq-7000 EPP PS boot device and peripherals The XPS generated PS constraint files are used by PlanAhead for the top-level design pin mapping

18 Zynq-7000 EPP Embedded Tool Flow 18 Hardware Flow ISE Programmable Logic User Programmable Logic Programmable Logic Implementation Processing System XPS PS Configuration (PS plus IP block in PL) IP Config System Wizards System Assembly Software Flow FSBL/BSP Generation SDK - Software Application Debug Application Development First Stage Boot Loader System Definition PS Register Initialization Data Programmable Logic Configuration Map of IP Location for Software

19 How is XPS Related to SDK? 19 Xilinx Platform Studio Software Development Kit Export Hardware Design Used to define hardware upon which software applications run Configure PS pin functionality and hardware settings Connect PL hardware to PS Auto-generate First Stage Boot Loader targeted to hardware design Build ARM executable and debug directly on target hardware

20 Handoff from Hardware to Software Flow 20 What is needed to enable the software team to run application code on the hardware? Source code to configure the PS DDR controller, selected peripherals, clock generation module, and the MIO Hardware description for FSBL and BSP generation Generated by XPS during export to SDK Component ps7_init.c ps7_init.h system.xml ps7_init.html Description Source files containing PS configuration setup Hardware platform description for FSBL and BSP generation Documentation of register level details, use as a reference alternative to browsing through initialization source code

21 Embedded Software Project Creation 21 Wizard driven project creation Choose an Empty Application template OR Select from example applications Quick tests of hardware & toolchain Base starting point for your own application

22 Application Build Process 22 Standard Eclipse build process using GNU toolchain

23 Debug Capabilities 23 GDB used as source and assembly-level debugger C Code Instruction Memory Location Assembly Instruction Equivalent

24 SDK Advanced Features 24 Editing Code completion C/C++ content assist Code hovering Code folding Refactoring File compare diff visualization Debugging Load data files before downloading application code Connect to the built-in terminal console Remote debug across Ethernet

25 Advantages of ARM DS-5 Tools 25 ARM Development Studio 5 (DS-5 ) toolchain Software development kit designed specifically for ARM architectures Replaces SDK in the software development flow ARM DS-5 Features DS-5 ARM Compiler Eclipse Compiler DS-5 Debugger IDE Debugger Customized Device Configuration Database Eclipse IDE Simulation Streamline Performance Analyzer Streamline Hardware Debug

26 DS-5 Integrated Development Environment 26 Customized Eclipse IDE, compatible with third party plug-ins Source editor features syntax colorization and code formatting for C/C++ and ARM/Thumb/Thumb2 assembly Includes a Remote System Explorer (RSE) perspective Custom visualization of variables and memory contents

27 DS-5 Debugger Capabilities 27 Debug machine code generated by ARMCC and GCC compilers Provides full system visibility of memory, CPU registers, peripheral registers, frame buffer Linux kernel and user space context awareness, including process and threads

28 DS-5 Streamline Performance Analyzer 28 Timeline view of processes and threads Visualize impact upon performance-related events Support for software events and performance counters Hierarchical CPU usage statistics aggregated by process and thread

29 Model-Based Design from MathWorks 29 MATLAB and Simulink System and Algorithm Design Automatically Generated Code (C & HDL) Implement Design Synthesis Host Compile Target Compile RTL Simulation Host Simulation Back Annotation Verification Functional Simulation Target Simulator Hardware Integrated workflow Increased collaboration Single test bench Optimal designs with short iteration cycles Unified design environment Fast & easy design entry & exploration Speedy simulation Unified design & test Cycle accurate, bit exact design Built-in analysis Shorter iteration cycles Cycle accurate, bit exact design Flexible automatic code generation Simulation of final design Test bench re-use Custom IP integration Integrated verification Reduce verification time Co-simulate with hardware in the loop

30 Model-Based Design Flow for Zynq-7000 EPP 30 Application MATLAB and Simulink Embedded Coder Automatic C/C++ Code Generation Application Processor Unit (APU) Memory Processing System MATLAB Zynq-7000 EPP Support S Data Interconnect HDL Coder Acceleration Block Acceleration Block Automatic RTL Code Generation Acceleration Block Programmable Logic

31 Simulink Support for Xilinx Zynq-7000 EPP 31 Field Oriented Control (FOC) Simulation in Simulink Embedded Coder generates C code for motor plant model executed on Cortex-A9 HDL Coder generates VHDL/Verilog for motor control model executed on FPGA Verify Zynq EPP target execution with Simulink via Gigabit Ethernet connection Gigabit Ethernet ZedBoard.org

32 Deciding Which Tools are Needed 32 SDK Zynq bare metal, RTOS, and Open Source Linux application development Integrated debug and profiling capability ARM target support available as part of ISE WebPack 14.1 DS-5 ARM bare metal, RTOS, and Open Source Linux application development ARM compiler provides best code size and performance SMP debug support Trace capability Lightweight Community Edition for small Android application developers MATLAB and Simulink Algorithm design using MATLAB and Simulink Implementation through Embedded Coder and HDL Coder Application Specialties: Signal Processing Image Processing Communications Control Design Test and Measurement Financial Modeling Computational Biology

34 Choosing the Optimal Operating System 34 What are your application requirements? Real-Time Performance High System Performance Standalone or Bare metal RTOS Micrium µc/os-iii Microsoft WEC7 BSP from Adeneo Open Source Linux AMP FreeRTOS Adeneo Android BSP SMP

35 Standalone or Bare Metal Execution 35 Application Code Loop ISR Interrupt Application Code Loop ARM0 Core ARM1 Core No operating system required Directly access hardware memory space Bypass Memory Management Unit (MMU) Tight control over execution but limited in functionality Preferred if software tasks are simple and repetitive Adding new tasks increases complexity rapidly

36 RTOS Solution 36 Tasks RTOS Kernel Tasks RTOS Kernel ARM0 Core RTOS Kernel ARM1 Core Managing real time performance factors offers determinism for real time applications Interrupt latency Scheduling latency Kernel service timing RTOS solutions provide framework for adding additional tasks and allow for software scalability

37 RTOS Availability for Zynq-7000 EPP 37 Commercial off the shelf solutions Available solutions to help meet different market segment needs Automotive Aerospace Consumer Defense Industrial Medical Scientific Avnet Embedded Software Store has commercially available solutions including Micrium μc/os-iii Open source solutions FreeRTOS is licensed under modified GPL

38 Linux Solution 38 Tasks Linux SMP Kernel ARM0 Core RTOS Kernel ARM1 Core Support for high system performance applications Symmetric multiprocessing Shared libraries Device drivers Memory management TCP/IP networking Commercially supported versions planned for Zynq

40 Linux Boot Process for Zynq-7000 EPP 40 ROM Boot Image 1 ROM Boot First Stage Boot Loader (FSBL) Internal Boot ROM Internal ROM 2 On-Chip Memory (OCM) U-Boot DDR Memory FSBL Linux Kernel U-Boot Non-Volatile Memory Linux Kernel DDR Memory On-Chip Memory (OCM) Zynq DDR Memory

41 First Stage Boot Loader 41 First Stage Boot Loader Functions Initialize Processing System blocks PLL External memory controller MIO Configure Programmable Logic with Bitstream Execute application code Provides for secure boot option Created directly from the SDK project template Initializes PS with XPS configuration

42 Creating the Zynq Boot Image 42 Zynq boot image contains FSBL, Bitstream, and second stage boot loader or application code

43 Files Required for Booting Application 43 DDR Memory Example of Zynq-7000 EPP booting Linux BOOT.BIN on SD Card Application Processor FSBL U-Boot PL Bitstream BOOT.BIN Programmable Logic Zynq-7000 zimage devicetree.dtb ramdisk8m.image.gz Boot Medium

45 Demo DS-5 Streamline Analysis 45 Demonstrates functionality and features of DS-5 Streamline application performance analysis tools Profiling Call path visualization Call graph Execution timeline Stack views Chart software events Ability to create performance counters Showcases ZedBoard running processor intense application

46 Next Steps 46 X-Fest course: Software Acceleration in Zynq X-Fest course: Designing Wireless Communication Systems in Xilinx FPGAs Try Zynq Open Source Linux: wiki.xilinx.com RTOS solutions on Avent Embedded Software Store: Download and Evaluate ARM Development Studio 5:

47 Next Steps 47 Learn more about the Zynq-7000 EPP Visit Purchase a Zynq development kit ZedBoard P/N: AES-Z7EV-7Z020-G Price: $395 Available: June 2012 ZC702 Evaluation Kit P/N: EK-Z7-ZC702-CES-G Price: $895 Available: June 2012 Zynq Video & Imaging Kit P/N: EK-Z7-VIDEO-CES-G Price: $1495 Available: June 2012

48 Next Steps 48 See the Zynq demos in the exhibit area ZedBoard Exhibits: Analog Devices, ARM, Avnet, Cypress, Maxim, Spansion, TE ZC702 Exhibits: Analog Devices, Avnet, Xilinx Contact your local Avnet FAE Application and architecture reviews Tools demo Attend additional Zynq training courses Avnet SpeedWay hands-on workshops Xilinx Authorized Training Partner courses

49 Next Steps 49 Coming in Fall Avnet SpeedWay Workshops 1-day hands-on Zynq workshops Intro to Zynq-7000 EPP Developing a Linux Application Using Zynq Software Defined Radio Development Using Zynq Video and Image Processing Using Zynq Visit Xilinx Training Courses In-depth, multi-day training courses Zynq EPP System Architecture Advanced Features and Techniques of Embedded Systems Software Design Visit for more details

50 Thank You Please Visit the Demo Area Tweet this event: #avtxfest

51 Appendix 51

52 Zynq-7000 Extensible Processing Platform 52 Embedded Application Requirement Single Chip Solution (ASIC) Application Processor Application Processor Single Chip Solution (EPP) Application Processor Logic Multi-Chip Solution (ASSP+FPGA) Application Processor Custom Logic Long lead time High NRE Low unit cost Programmable Logic Software acceleration Peripheral Customization Common platform Programmable Logic Multiple chips Bandwidth limitations Off the shelf

53 Features of the ARM Cortex-A9 MPCore 53 ARM Cortex-A Series Application-class processor targets peak performance demands while reaching low power goals Dual Core Architecture Delivers highly scalable performance and can offer high levels of design flexibility NEON/FPU Engine Cortex-A9 MPCore Instruction Cache Data Cache NEON/FPU Engine Cortex-A9 MPCore Instruction Cache Data Cache 512KB L2 Cache Snoop Control Unit 256KB OCM Interrupt Controller, Timers, DMA, and Debug

54 Application Specific Optimizations 54 Feature High-Efficiency Superscalar Pipeline NEON Media Processing Engine Floating-Point Unit Optimized Level 1 Caches Thumb-2 Technology TrustZone Technology L2 Cache Controller Program Trace Macrocell and CoreSight Design Kit Benefit Industry leading performance while also maintaining low power for lower cost packaging and operation Accelerating media and signal processing functions for increased application specific performance Provides acceleration for both single and double precision scalar Floating-Point operations Optimized L1 cache access latency techniques to maximize performance and minimize power consumption Peak performance of traditional ARM code also provides up to a 30% reduction in memory for storing instructions Ensures reliable implementation of security applications ranging from DRM to electronic payment Provides low latency and high bandwidth access to up to 2 MB of cached memory in high frequency designs. Provides software developers with the ability to nonobtrusively trace the execution history of multiple cores

55 Application Specific Optimizations 55 Feature Benefit Floating-Point Unit (FPU) NEON Media Processing Engine (MPE) Program Trace Macrocell (PTM) Provides acceleration for both single and double precision scalar Floating-Point operations Provide a quad-mac and additional 64-bit and 128-bit register set supporting a rich set of SIMD operations Provides software developers with the ability to nonobtrusively trace the execution history of multiple cores How are these features relevant to software development? FPU Enhance solutions using: Rich graphics 3D imaging Scientific computation MPE Further performance acceleration of: Media processing Signal processing PTM Debug visibility over: All code branches Program flow changes

56 AMP vs. SMP Solutions 56 Asymmetric Multi-Processing (AMP) Multiple CPUs which may be of different architectures Each CPU may run its own OS instance but not necessarily homogeneously Software abstraction of shared memory space often used as a communication facility between the CPUs Symmetric Multi-Processing (SMP) Multiple CPUs of the same architectures Single OS instance is used which runs on all the CPUs, dividing work between them Shared memory space used to coordinate execution between the CPUs and share data

57 Software Design for Cortex-A9 MPCore 57 Multiple concurrent execution threads require appropriate resource management Single Core Execution ARM0 Core Hardware Peripheral Dual Core Execution ARM0 Core ARM1 Core Hardware Peripheral Operating systems can help solve these challenges through either AMP or SMP strategies

58 AMP and SMP on Zynq-7000 EPP 58 AMP Tasks Tasks Linux Kernel RTOS Kernel Shared Memory Space ARM0 Core ARM1 Core SMP Tasks Linux Kernel Shared Memory Space ARM0 Core ARM1 Core

59 Linux Support for Zynq-7000 EPP 59 Advantages of Linux Broad use as a desktop, server, and embedded OS Feature-rich Symmetric multiprocessing Preemptive multitasking Shared libraries Device drivers Memory management IP networking Support for multiple file systems Tasks Kernel CPU Memory Devices Commercially supported versions planned for Zynq Runtime images suitable for embedded systems

60 Linux Root File System for Zynq 60 Contains files critical to system execution Root File System Applications Configuration files Data files Device files Mounted file systems Shared libraries Mounted right after kernel initialization completes Contains scripts for the first process to run: init Different media types can be used: RAM, SD card, SPI Flash, network file system Pre-built ramdisk image provided for reference Steps for building custom root file system available on the Xilinx Wiki:

61 Demo SDK OProfile Analysis 61 Demonstrates OProfile analysis tool capability from within SDK Linux OS-wide CPU utilization Linux OS-wide CPU utilization with library info Application-level call-graph view Application-level Assembly view Showcases ZedBoard running processor intense application