How To Power A Power Supply On A Powerline (Power Supply) (Power Source) (Wired) (Wire) (Powered) (Unmanned) (Electric) (Plastipower) (Motor) (Power)

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Bruno Hall
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1 Preferred Device Silicon Bidirectionl Thyristors Designed primrily for full-wve c control pplictions, such s light dimmers, motor controls, heting controls nd power supplies; or wherever full-wve silicon gte controlled solid-stte devices re needed. Tric type thyristors switch from blocking to conducting stte for either polrity of pplied node voltge with positive or negtive gte triggering. Sensitive Gte Triggering Uniquely Comptible for Direct Coupling to TTL, HTL, CMOS nd Opertionl Amplifier Integrted Circuit Logic Functions Gte Triggering 4 Mode,B, 2N6073A,B, 2N6075A,B Blocking Voltges to 600 Volts All Diffused nd Glss Pssivted Junctions for Greter Prmeter Uniformity nd Stbility Smll, Rugged, Thermopd Construction for Low Therml Resistnce, High Het Dissiption nd Durbility Device Mrking: Device Type, e.g.,, Dte Code MAXIMUM RATINGS (TJ = 25 C unless otherwise noted) Rting Symbol Vlue Unit *Pek Repetitive Off-Stte Voltge(1) (TJ = 40 to 110 C, Sine Wve, 50 to 60 Hz, Gte Open),B 2N6073A,B 2N6075A,B *On-Stte RMS Current (TC = 85 C) Full Cycle Sine Wve 50 to 60 Hz *Pek Non repetitive Surge Current (One Full cycle, 60 Hz, TJ = +110 C) Circuit Fusing Considertions (t = 8.3 ms) *Pek Gte Power (Pulse Width µs, TC = 85 C) *Averge Gte Power (t = 8.3 ms, TC = 85 C) VDRM, VRRM Volts IT(RMS) Amps ITSM 30 Amps I2t 3.7 A2s PGM 10 Wtts PG(AV) Wtt TRIACS 4 AMPERES RMS 200 thru 600 VOLTS MT G TO 225AA (formerly TO 126) CASE 077 STYLE 5 PIN ASSIGNMENT Min Terminl 1 Min Terminl 2 Gte *Pek Gte Voltge (Pulse Width µs, TC = 85 C) VGM 5.0 Volts *Operting Junction Temperture Rnge TJ 40 to +110 *Storge Temperture Rnge Tstg 40 to +150 Mounting Torque (6-32 Screw)(2) 8.0 in. lb. *Indictes JEDEC Registered Dt. (1) VDRM nd VRRM for ll types cn be pplied on continuous bsis. Blocking voltges shll not be tested with constnt current source such tht the voltge rtings of the devices re exceeded. (2) Torque rting pplies with use of compression wsher. Mounting torque in excess of 6 in. lb. does not pprecibly lower cse-to-sink therml resistnce. Min terminl 2 nd hetsink contct pd re common. C C ORDERING INFORMATION Device Pckge Shipping TO225AA 500/Box 2N6071B TO225AA 500/Box 2N6073A TO225AA 500/Box 2N6073B TO225AA 500/Box 2N6075A TO225AA 500/Box 2N6075B TO225AA 500/Box Preferred devices re recommended choices for future use nd best overll vlue. Semiconductor Components Industries, LLC, 2000 My, 2000 Rev. 3 1 Publiction Order Number: 2N6071/D

Sensitive Gte Triggering Uniquely Comptible for Direct Coupling to TTL, HTL, CMOS nd Opertionl Amplifier Integrted Circuit Logic Functions Gte Triggering 4 Mode,B, 2N6073A,B, 2N6075A,B Blocking

2 /B THERMAL CHARACTERISTICS Chrcteristic Symbol Mx Unit *Therml Resistnce, Junction to Cse RθJC 3.5 C/W Therml Resistnce, Junction to Ambient RθJA 75 C/W Mximum Led Temperture for Soldering Purposes 1/8 from Cse for 10 Seconds TL 260 C ELECTRICAL CHARACTERISTICS (TC = 25 C unless otherwise noted; Electricls pply in both directions) Chrcteristic Symbol Min Typ Mx Unit OFF CHARACTERISTICS *Pek Repetitive Blocking Current (VD = Rted VDRM, VRRM; Gte Open) TJ = 25 C TJ = 110 C ON CHARACTERISTICS *Pek On-Stte Voltge(1) (ITM = 6 A Pek) IDRM, IRRM 10 2 µa VTM 2 Volts *Gte Trigger Voltge (Continuous dc) (Min Terminl Voltge = 12 Vdc, RL = 100 Ohms, TJ = 40 C) All Qudrnts Gte Non Trigger Voltge (Min Terminl Voltge = 12 Vdc, RL = 100 Ohms, TJ = 110 C) All Qudrnts *Holding Current (Min Terminl Voltge = 12 Vdc, Gte Open, Inititing Current = 1 Adc) Turn-On Time (ITM = 14 Adc, IGT = 100 dc) (TJ = 40 C) (TJ = 25 C) VGT VGD IH Volts Volts tgt 1.5 µs QUADRANT (Mximum Vlue) Gte Trigger Current (Continuous dc) (Min Terminl Voltge = 12 Vdc, RL = 100 ohms) Type TJ I II III IV +25 C N6073A 2N6075A 40 C DYNAMIC CHARACTERISTICS Criticl Rte of Rise of Commuttion VDRM, TJ = 85 C, Gte Open, ITM = 5.7 A, Exponentil Wveform, Commutting di/dt = A/ms *Indictes JEDEC Registered Dt. (1) Pulse Test: Pulse Width ms, Duty Cycle 2%. 2N6071B +25 C N6073B 2N6075B 40 C dv/dt(c) 5 V/µs 2

Electricls pply in both directions) Chrcteristic Symbol Min Typ Mx Unit OFF CHARACTERISTICS *Pek Repetitive Blocking Current (VD = Rted VDRM, VRRM; Gte Open) TJ = 25 C TJ = 110 C ON CHARACTERISTICS

3 /B SAMPLE APPLICATION: TTL-SENSITIVE GATE 4 AMPERE TRIAC TRIGGERS IN MODES II AND III 0 V VEE 14 MC VEE = 5.0 V Ω LOAD 115 VAC 60 Hz Trigger devices re recommended for gting on Trics. They provide: 1. Consistent predictble turn-on points. 2. Simplified circuitry. 3. Fst turn-on time for cooler, more efficient nd relible opertion. Voltge Current Chrcteristic of Trics (Bidirectionl Device) + Current Symbol VDRM IDRM VRRM IRRM Prmeter Pek Repetitive Forwrd Off Stte Voltge Pek Forwrd Blocking Current Pek Repetitive Reverse Off Stte Voltge Pek Reverse Blocking Current IRRM t VRRM on stte IH VTM Qudrnt 1 MinTerminl 2 + VTM IH Mximum On Stte Voltge Holding Current IH off stte + Voltge IDRM t VDRM Qudrnt 3 MinTerminl 2 V TM 3

Fst turn-on time for cooler, more efficient nd relible opertion.

4 /B Qudrnt Definitions for Tric MT2 POSITIVE (Positive Hlf Cycle) + (+) MT2 (+) MT2 Qudrnt II ( ) IGT GATE (+) IGT GATE Qudrnt I REF REF IGT + IGT ( ) MT2 ( ) MT2 Qudrnt III ( ) IGT GATE (+) IGT GATE Qudrnt IV REF REF MT2 NEGATIVE (Negtive Hlf Cycle) All polrities re referenced to. With in phse signls (using stndrd AC lines) qudrnts I nd III re used. SENSITIVE GATE LOGIC REFERENCE IC Logic Functions Firing Qudrnt I II III IV TTL HTL CMOS (NAND) 2N6071B 2N6071B CMOS (Buffer) 2N6071B 2N6071B Opertionl Amplifier Zero Voltge Switch 4

re referenced to. With in phse signls (using stndrd AC lines) qudrnts I nd III re used.

5 /B T C, CASE TEMPERATURE ( C) α α = dc T C, CASE TEMPERATURE ( C) α = dc 90 α = CONDUCTION ANGLE 70 0 IT(AV), AVERAGE ON-STATE CURRENT (AMP) α = CONDUCTION ANGLE 70 0 IT(RMS), RMS ON-STATE CURRENT (AMP) Figure 1. Averge Current Derting Figure 2. RMS Current Derting P (AV), AVERAGE POWER (WATTS) α = CONDUCTION ANGLE α = dc P (AV), AVERAGE POWER (WATTS) α = CONDUCTION ANGLE 120 α = dc IT(AV), AVERAGE ON-STATE CURRENT (AMP) Figure 3. Power Dissiption IT(RMS), RMS ON-STATE CURRENT (AMP) Figure 4. Power Dissiption, GATE TRIGGER VOLTAGE (NORMALIZED) VGT OFF-STATE VOLTAGE = 12 Vdc ALL MODES TJ, JUNCTION TEMPERATURE ( C) 100 Figure 5. Typicl Gte Trigger Voltge , GATE TRIGGER CURRENT (NORMALIZED) IGT 0.7 OFF-STATE VOLTAGE = 12 Vdc ALL MODES TJ, JUNCTION TEMPERATURE ( C) Figure 6. Typicl Gte Trigger Current 5

0 α = CONDUCTION ANGLE α = 30 60 90 120 180 dc P (AV), AVERAGE POWER (WATTS) 8.0 6.0 α = CONDUCTION ANGLE 120 α = 180 90 60 dc 30 0 0 0 0 IT(AV), AVERAGE ON-STATE CURRENT (AMP) Figure 3.

6 /B ITM, ON-STATE CURRENT (AMP) TJ = 110 C TJ = 25 C IH, HOLDING CURRENT (NORMALIZED) TJ, JUNCTION TEMPERATURE ( C) GATE OPEN APPLIES TO EITHER DIRECTION Figure 8. Typicl Holding Current VTM, ON-STATE VOLTAGE (VOLTS) PEAK SINE WAVE CURRENT (AMP) TJ = 40 to +110 C f = 60 Hz NUMBER OF FULL CYCLES Figure 7. Mximum On Stte Chrcteristics Figure 9. Mximum Allowble Surge Current ZθJC(t), TRANSIENT THERMAL IMPEDANCE ( C/W) MAXIMUM TYPICAL k k 5.0 k 10 k t, TIME (ms) Figure 10. Therml Response 6

0 VTM, ON-STATE VOLTAGE (VOLTS) PEAK SINE WAVE CURRENT (AMP) 34 32 30 28 26 24 22 TJ = 40 to +110 C f = 60 Hz 20 18 16 14 5.0 7.0 10 NUMBER OF FULL CYCLES Figure 7.

7 /B PACKAGE DIMENSIONS TO 225AA (formerly TO 126) CASE ISSUE W H Q B U F A K V G S D 2 PL M C J R 0.25 (0.010) M A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.39 BSC H J K M 5 TYP 5 TYP Q R S U V (0.010) M A M B M STYLE 5: PIN 1. MT 1 2. MT 2 3. GATE 7

50 7.74 C 0.095 0.105 2.42 2.66 D 0.020 0.026 1 0.66 F 0.115 0.130 2.93 3.30 G 0.094 BSC 2.39 BSC H 0.050 0.095 1.27 2.41 J 0.015 0.025 9 0.63 K 75 0.655 14.

8 /B ON Semiconductor nd re trdemrks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to mke chnges without further notice to ny products herein. SCILLC mkes no wrrnty, representtion or gurntee regrding the suitbility of its products for ny prticulr purpose, nor does SCILLC ssume ny libility rising out of the ppliction or use of ny product or circuit, nd specificlly disclims ny nd ll libility, including without limittion specil, consequentil or incidentl dmges. Typicl prmeters which my be provided in SCILLC dt sheets nd/or specifictions cn nd do vry in different pplictions nd ctul performnce my vry over time. All operting prmeters, including Typicls must be vlidted for ech customer ppliction by customer s technicl experts. SCILLC does not convey ny license under its ptent rights nor the rights of others. SCILLC products re not designed, intended, or uthorized for use s components in systems intended for surgicl implnt into the body, or other pplictions intended to support or sustin life, or for ny other ppliction in which the filure of the SCILLC product could crete sitution where personl injury or deth my occur. Should Buyer purchse or use SCILLC products for ny such unintended or unuthorized ppliction, Buyer shll indemnify nd hold SCILLC nd its officers, employees, subsidiries, ffilites, nd distributors hrmless ginst ll clims, costs, dmges, nd expenses, nd resonble ttorney fees rising out of, directly or indirectly, ny clim of personl injury or deth ssocited with such unintended or unuthorized use, even if such clim lleges tht SCILLC ws negligent regrding the design or mnufcture of the prt. SCILLC is n Equl Opportunity/Affirmtive Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literture Fulfillment: Literture Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colordo USA Phone: or Toll Free USA/Cnd Fx: or Toll Free USA/Cnd Emil: [email protected] Fx Response Line: or Toll Free USA/Cnd N. Americn Technicl Support: Toll Free USA/Cnd EUROPE: LDC for ON Semiconductor Europen Support Germn Phone: (+1) (M F 1:00pm to 5:00pm Munich Time) Emil: ONlit [email protected] French Phone: (+1) (M F 1:00pm to 5:00pm Toulouse Time) Emil: ONlit [email protected] English Phone: (+1) (M F 12:00pm to 5:00pm UK Time) Emil: [email protected] EUROPEAN TOLL FREE ACCESS*: *Avilble from Germny, Frnce, Itly, Englnd, Irelnd CENTRAL/SOUTH AMERICA: Spnish Phone: (Mon Fri 8:00m to 5:00pm MST) Emil: ONlit [email protected] ASIA/PACIFIC: LDC for ON Semiconductor Asi Support Phone: (Tue Fri 9:00m to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singpore: Emil: ONlit [email protected] JAPAN: ON Semiconductor, Jpn Customer Focus Center Nishi Gotnd, Shingw ku, Tokyo, Jpn Phone: Emil: [email protected] ON Semiconductor Website: For dditionl informtion, plese contct your locl Sles Representtive. 8 2N6071/D

circuit, nd specificlly disclims ny nd ll libility, including without limittion specil, consequentil or incidentl dmges.

C106 Series. Sensitive Gate Silicon Controlled Rectifiers

C106 Series. Sensitive Gate Silicon Controlled Rectifiers C6 Series Sensitive Gate Silicon Controlled Rectifiers Reverse Blocking Thyristors Glassivated PNPN devices designed for high volume consumer applications such as temperature, light, and speed control;