NCP432, NCP A Ultra-Small Controlled Load Switch with Auto-Discharge Path

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1 1.5 Ultra-Small Controlled Load Switch with uto-discharge Path The NCP2 and NCP are a low Ron MOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, due to a current consumption optimization with PMOS structure, leakage currents are eliminated by isolating connected IC s on the battery when not used. Output discharge path is also embedded to eliminate residual voltages on the output (NCP only). Proposed in wide input voltage range from 1. V to.6 V, and a very small.76 x.76 mm WLCSP,. mm pitch. Features 1 V.6 V Operating Range 5 m P MOSFET at 1.8 V DC Current up to 1.5 Output uto discharge (NCP) ctive High Pin WLCSP.76 x.76 mm These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant B WLCSP CSE 567FJ XX = V or T PINOUT 1 2 OUT GND IN MRKING DIGRM XX Typical pplications Mobile Phones Tablets Digital Cameras GPS Portable Devices (Top View) ORDERING ND MRKING INFORMTION See detailed ordering and shipping information on page 6 of this data sheet. V+ LS DCDC Converter or 2 NCP IN OUT 1 Platform IC n LDO B2 GND B1 x Figure 1. Typical pplication Circuit Semiconductor Components Industries, LLC, 21 December, 21 Rev. 1 1 Publication Order Number: NCP2/D

2 PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description IN 2 POWER Load switch input voltage; connect a 1 F or greater ceramic capacitor from IN to GND as close as possible to the IC. GND B1 POWER Ground connection. B2 INPUT Enable input, logic high turns on power switch. OUT 1 OUTPUT Load switch output; connect a 1 F ceramic capacitor from OUT to GND as close as possible to the IC is recommended. BLOCK DIGRM Figure 2. Block Diagram 2

3 MXIMUM RTINGS Rating Symbol Value Unit IN, OUT,, Pins: From IN to OUT Pins: Input/Output V, V IN,. to +. V V IN, to +. V Maximum Junction Temperature T J to C Storage Temperature Range T STG to + 15 C Human Body Model (HBM) ESD Rating are (Notes 1 and 2) ESD HBM 7 V Machine Model (MM) ESD Rating are (Notes 1 and 2) ESD MM 25 V Charge Device Model (CDM) ESD Rating are (Notes 1 and 2) ESD CDM 2 V Latch up protection (Note ) Pins IN, OUT, LU 1 m Moisture Sensitivity (Note ) MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. ccording to JEDEC standard JESD This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±7. kv per JEDEC standard: JESD22 11 for all pins. Machine Model (MM) ±25 V per JEDEC standard: JESD for all pins. Charge Device Model (CDM) ±2. kv per JEDEC standard: JESD22 C11 for all pins.. Latch up Current Maximum Rating: ±1 m per JEDEC standard: JESD78 class II.. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J STD 2. OPERTING CONDITIONS Symbol Parameter Conditions Min Typ Max Unit V IN Operational Power Supply 1..6 V V Enable Voltage.6 T mbient Temperature Range C C IN Decoupling input capacitor 1 F C OUT Decoupling output capacitor 1 F R J Thermal Resistance Junction to ir WLCSP package (Note 5) 15 C/W I OUT Maximum DC current 1.5 P D Power Dissipation Rating (Note 6) T 25 C WLCSP package.5 W 5. The R J is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (P D ) is given by the following formula: T = 85 C WLCSP package.2 W

4 ELECTRICL CHRCTERISTICS Min & Max Limits apply for T between C to +85 C for V IN between 1. V to.6 V (Unless otherwise noted). Typical values are referenced to T = + 25 C and V IN =. V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit POWER SWITCH R DS(on) Static drain source on state resistance V IN =.6 V V IN =. V V IN = 1.8 V T = 25 C, I = 2 m (Note 8) 5 T = 85 C 55 T = 25 C, I = 2 m 7 T = 85 C 6 T = 25 C, I = 2 m 5 T = 85 C 8 V IN = 1.2 V T = 25 C, I = 2 m 1 T = 85 C 15 V IN = 1.1 V T = 25 C, I = 1 m 12 R DIS Output discharge path = low V IN =. V, NCP only 65 9 T R T F Output rise time T V IN =.6 V on Gate turn on Gate turn on + Output rise time s T en Output fall time Enable time m C LOD = 1 F, R LOD = 25 (Note 7) from 1% to 9% of 5 2 s C LOD = 1 F, R LOD = 25 (Note 7) From low to high to 1% s s T dis Disable time From high to low to = 9% of fully on s V IH High level input voltage.9 V V IL Low level input voltage.5 V QUIESCT CURRT I Q Current consumption V IN =. V, = low, No load.1.6 V IN =. V, = high, No load Parameters are guaranteed for C LOD and R LOD connected to the OUT pin with respect to the ground 8. Guaranteed by design and characterization, not production tested. TIMINGS V IN T T R T DIS T F T ON T OFF Figure. Enable, Rise and Fall Time

5 TYPICL CHRCTERISTICS Temp = C Temp = 25 C Temp = 85 C Temp = C Temp = 25 C Temp = 85 C I IN ( ) I IN ( ) Figure. Standby Current versus Temperature 1 2 Figure 5. Quiescent Current versus Temperature 25 I LOD = 1 m 5 I LOD = 1 m C C 5 C 25 C 25 C 85 C R DS(on) (m ) R DS(on) (m ) Figure 6. R DS(on) versus V IN, 25 C, 1 m Load 1 2 Figure 7. R DS(on) versus Temperature, 1 m Load FUNCTIONL DESCRIPTION Overview The NCP2 NCP are high side P channel MOSFET power distribution switch designed to isolate ICs connected on the battery in order to save energy. The part can be turned on, with a range of battery from 1. V to.6 V. Enable Input Enable pin is an active high. The path is opened when pin is tied low (disable), forcing P MOS switch off. The IN/OUT path is activated with a minimum of Vin of 1. V and forced to high level. The auto discharge is activated when pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as pin is set at low level and V IN > 1. V. In order to limit the current across the internal discharge N MOSFET, the typical value is set at 65. Cin and Cout Capacitors IN and OUT, 1 F, at least, capacitors must be placed as close as possible the part for stability improvement. uto Discharge (NCP only) NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. 5

6 PPLICTION INFORMTION Power Dissipation Main contributor in term of junction temperature is the power dissipation of the power MOSFET. ssuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: P D R DS(on) IOUT 2 P D R DS(on) I OUT = Power dissipation (W) = Power MOSFET on resistance ( ) = Output current () T J R J T = Junction temperature ( C) = Package thermal resistance ( C/W) = mbient temperature ( C) PCB Recommendations The NCP2 NCP integrate an up to 1.5 rated PMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, especially around IN and OUT pins, the R J of the package can be decreased, allowing higher power dissipation. T J P D R J T ORDERING INFORMTION Device Marking Package Shipping NCP2FCT2G V WLCSP (Pb Free) / Tape & Reel NCPFCT2G T WLCSP (Pb Free) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D. 6

7 PCKGE DIMSIONS WLCSP,.76x.76 CSE 567FJ ISSUE O PIN 1 REFERCE 2X 2X NOTE.5 C.5 C.5 C 1 D ÈÈ.5 C TOP VIEW SIDE VIEW 2 B E C SETING PLNE NOTES: 1. DIMSIONING ND TOLERNCING PER SME Y1.5M, CONTROLLING DIMSION: MILLIMETERS.. COPLNRITY PPLIES TO SPHERICL CROWNS OF SOLDER BLLS. MILLIMETERS DIM MIN MX REF b.2.28 D.76 BSC E.76 BSC e. BSC RECOMMDED SOLDERING FOOTPRINT* 1 PCKGE OUTLINE X b.5 C B. C B e e. PITCH X.2. PITCH DIMSIONS: MILLIMETERS 1 2 BOTTOM VIEW *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ffirmative ction Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICTION ORDERING INFORMTION LITERTURE FULFILLMT: Literature Distribution Center for ON Semiconductor P.O. Box 516, Denver, Colorado 8217 US Phone: or 8 86 Toll Free US/Canada Fax: or Toll Free US/Canada [email protected] N. merican Technical Support: Toll Free US/Canada Europe, Middle East and frica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCP2/D