TISP9110LDM Overvoltage Protector

Transcription

1 *RoHS COMPLINT TISP9110LDM INTEGRTED COMPLEMENTRY BUFFERED-GTE SCRS FOR DUL POLRITY SLIC OEROLTGE PROTECTION TISP9110LDM Overvoltage Protector High Performance Protection for SLICs with +ve and -ve Battery Supplies Wide -110 to +110 Programming Range Low 5 m max. Gate Triggering Current Dynamic Protection Performance Specified for International Surge Waveshapes pplications include: Wireless Local Loop ccess Equipment Regenerated POTS OIP pplications Rated for International Surge Wave Shapes 8-SOIC (210 mil) Package (Top iew) (Tip or Ring) Line (- (BT) ) G1 (+ (BT) ) G2 (Ring or Tip) Line 1 8 NC NC NC - No internal connection Terminal typical application names shown in parenthesis MD-8SOIC(210)-003-a Wave Shape Standard 2/10 GR-1089-CORE /700 ITU-T K.20/21/ /1000 GR-1089-CORE 30 Device Symbol Line... UL Recognized Component Description The TISP9110LDM is a programmable overvoltage protection device designed to protect modern dual polarity supply rail ringing SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line. Overvoltages can be caused by lightning, a.c. power contact and induction. Four separate protection structures are used; two positive and two negative to provide optimum protection during Metallic (Differential) and Longitudinal (Common Mode) protection conditions in both polarities. Dynamic protection performance is specified under typical international surge waveforms from Telcordia GR CORE, ITU-T K.44 and YD/T 950. G1 Line G2 SD-TISP9-001-a The TISP9110LDM is programmed by connecting the G1 and G2 gate terminals to the negative (- (BT) ) and positive (+ (BT) ) SLIC Battery supplies respectively. This creates a protector operating at typically +1.4 above + (BT) and -1.4 below - (BT) under a.c. power induction and power contact conditions. The protector gate circuitry incorporates 4 separate buffer transistors designed to provide independent control for each protection element. The gate buffer transistors minimize supply regulation issues by reducing the gate current drawn to around 5 m, while the high voltage base emitter structures eliminate the need for expensive reverse bias protection gate diodes. The TISP9110LDM is rated for common surges contained in regulatory requirements such as ITU-T K.20, K.45, Telcordia GR-1089-CORE, YD/T 950. By the use of appropriate overcurrent protection devices such as the Bourns Multifuse and Telefuse devices, circuits can be designed to comply with modern telecom standards. How To Order Device Package Carrier For Lead Free Termination Finish Order s Marking Code Standard Quantity TISP9110LDM 8-SOIC (210 mil) Embossed Tape Reeled TISP9110LDMR-S 9110L 2000 *RoHS Directive 2002/95/EC Jan including nnex

2 bsolute Maximum Ratings, T = 25 C (Unless Otherwise Noted) Repetitive peak off-state voltage G1(Line) =0, G2 +5 G2(Line) =0, G1-5 Non-repetitive peak impulse current (see Notes 1, 2, 3 and 4) 2/10 µs (Telcordia GR-1089-CORE) 5/310 µs (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700 µs) 10/1000 µs (Telcordia GR-1089-CORE) Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 5) 0.2 s 1 s 900 s Rating Symbol alue Unit DRM ±100 ±45 ± Maximum negative battery supply voltage G1M -110 Maximum positive battery supply voltage G2M +110 Maximum differential battery supply voltage (BT)M 220 Junction temperature T J -40 to +150 C Storage temperature range T stg -65 to +150 C NOTES: 1. Initially the device must be in thermal equilibrium with T J = 25 C. The surge may be repeated after the device returns to its initial conditions. 2. The rated current values may be applied to either of the Line to terminal pairs. dditionally, both terminal pairs may have their rated current values applied simultaneously (in this case the terminal current will be twice the rated current value of a single terminal pair). 3. Rated currents only apply if pins 6 & 7 () are connected together. 4. pplies for the following bias conditions: G1 = -20 to -110, G2 = 0 to EI/JESD51-2 environment and EI/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Electrical Characteristics for any Section, T = 25 C (Unless Otherwise Noted) Parameter Test Conditions Min Typ Max Unit Off-state current D = DRM, G1(Line) = 0, G2 +5 D = DRM, G2(Line) = 0, G1-5 T = 25 C T = 85 C T = 25 C T = 85 C I G1(Line) Negative-gate leakage current G1(Line) = µ I G2(Line) Positive-gate leakage current G2(Line) = µ G1L(BO) Gate - Line impulse breakover voltage G1 = -100, I T = -100 (see Note 6) G1 = -100, I T = -30 G2L(BO) Gate - Line impulse breakover voltage G2 = +100, I T = +100 (see Note 6) G2 = +100, I T = +30 2/10 µs 10/1000 µs 2/10 µs 10/1000 µs I H - Negative holding current G1 = -60, I T = -1, di/dt = 1 /ms -150 m I G1T Negative-gate trigger current I T =-5, t p(g) 20 µs, G1 = m I G2T Positive-gate trigger current I T =5, t p(g) 20 µs, G2 = 60-5 m C O Line - off-state capacitance f = 1 MHz, D = -3, G1 & G2 open circuit 32 pf NOTE: 6. oltage measurements should be made with an oscilloscope with limited bandwidth (20 MHz) to avoid high frequency noise µ

3 Thermal Characteristics, T = 25 C (Unless Otherwise Noted) R θj NOTE Parameter Test Conditions Min Typ Max Unit EI/JESD51-7 PCB, EI/JESD51-2 Environment, P Junction to ambient thermal resistance TOT = 4 W 55 C/W (See Note 7) 7. EI/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Parameter Measurement Information +i Quadrant I Switching Characteristic I TRM (BO) I H -v G1 D G2 +v D I H (BO) I TRM Quadrant III Switching Characteristic -i PM-TISP9-001-a Figure 1. oltage-current Characteristic Unless Otherwise Noted, ll oltages are Referenced to the Terminal

4 Typical Characteristics Thermal Information C o - Off-state Capacitance - pf OFF-STTE CPCITNCE vs OFF-STTE OLTG E T J = 25 C d = 1 rms TC-TISP9-001-a NON-REPETITIE PEK ON-STTE CURRENT vs CURRENT DURTION D - Off-state oltage - t - Current Duration - s Figure 2. Figure 3. (t) - Non-Repetitive Peak On-State Current TI-TISP9-001-a GEN = 600 rms, 50/60 Hz R GEN = 1.4* GEN /(t) EI/JESD51-2 ENIRONMENT EI/JESD51-7 PCB, T = 25 C SIMULTNEOUS OPERTION OF R ND T TERMINLS. GROUND TERMINL CURRENT = 2 x (t)

5 PPLICTIONS INFORMTION Tip Overcurrent Protection SLIC PROTECTOR SLIC C1 220 nf C2 220 nf Ring TISP9110LDM + BT D1 - BT Figure 4. Typical pplication Diagram GR-1089-Core Intra Building Overcurrent Protection 1 GR-1089-CORE Overcurrent Protection 2 ITU-T K20 (Basic) Overcurrent Protection 3 ITU-T K20 (Enhanced) Overcurrent Protection 4 F1a B0500T MF-SM Ω CPTC Telcordia GR-1089-CORE Issue 3 compliant LFR (Custom) * GDT (Bourns) F1b B0500T MF-SM Ω CPTC Figure 5. Typical Overcurrent Protection * greed Primary I-TISP9-001-a TISP is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office. Bourns is a registered trademark of Bourns, Inc. in the U.S. and other countries.