MC14008B. 4-Bit Full Adder

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1 4-Bit Full Adder The MC4008B 4bit full adder is constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure. This device consists of four full adders with fast internal lookahead carry output. It is useful in binary addition and other arithmetic applications. The fast parallel carry output bit allows highspeed operation when used with other adders in a system. Features LookAhead Carry Output Diode Protection on All Inputs All Outputs Buffered Supply Voltage Range =.0 to 8 Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range PinforPin Replacement for CD4008B This Device is PbFree and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to V SS ) Symbol Parameter Value Unit DC Supply Voltage Range 0.5 to +8.0 V V in, V out Input or Output Voltage Range (DC or Transient) 0.5 to V I in, I out P D Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note ) ± ma 500 mw T A Ambient Temperature Range 55 to +5 C T stg Storage Temperature Range 65 to +0 C T L Lead Temperature (8Second Soldering) 60 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Temperature Derating: D/DW Package: 7.0 mw/ C From 65 C To 5 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or ). Unused outputs must be left open. SOIC D SUFFIX CASE 75B MARKING DIAGRAM A WL, L YY, Y WW, W G PIN ASSIGNMENT V SS BG AWLYWW = Assembly Location = Wafer Lot = Year = Work Week = PbFree Indicator ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. 4 9 Semiconductor Components Industries, LLC, 04 July, 04 Rev. 8 Publication Order Number: MC4008B/D

2 TRUTH TABLE (One Stage) B A S BLOCK DIAGRAM HIGH-SPEED PARALLEL CARRY C4 C C = PIN V SS = PIN 8 ORDERING INFORMATION Device Package Shipping MC4008BDRG SOIC (PbFree) 500 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D.

3 ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) 55 C 5 C 5 C Characteristic Output Voltage V in = or 0 V in = 0 or Input Voltage (V O = 4.5 or 0.5 ) (V O = 9.0 or.0 ) (V O =.5 or.5 ) 0 Level Level 0 Level (V O = 0.5 or 4.5 ) Level (V O =.0 or 9.0 ) (V O =.5 or.5 ) Output Drive Current (V OH =.5 ) Source (V OH = 4.6 ) (V OH = 9.5 ) (V OH =.5 ) (V OL = 0.4 ) Sink (V OL = 0.5 ) (V OL =.5 ) Symbol V OL V OH V IL V IH I OH I OL Min Max Min Typ (Note ) Max Min Max Input Current I in ±0. ± ±0. ±.0 Adc Input Capacitance (V in = 0) Quiescent Current (Per Package) Total Supply Current (Notes & 4) (Dynamic plus Quiescent, Per Package) ( = 50 pf on all outputs, all buffers switching) pf I DD I T I T = (.7 A/kHz) f + I DD I T = (.4 A/kHz) f + I DD I T = ( A/kHz) f + I DD Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance.. The formulas given are for the typical characteristics only at 5 C. 4. To calculate total supply current at loads other than 50 pf: I T ( ) = I T (50 pf) + ( 50) Vfk where: I T is in A (per package), in pf, V = ( V SS ) in volts, f in khz is input frequency, and k = Unit madc madc Adc Adc

4 SWITCHING CHARACTERISTICS (Note 5) ( = 50 pf, T A = 5 C) Typ Characteristic Output Rise and Fall Time t TLH, t THL = (.5 ns/pf) + 5 ns t TLH, t THL = (0.75 ns/pf) +.5 ns t TLH, t THL = (0.55 ns/pf) ns Symbol t TLH, t THL Min (Note 6) Max Unit ns Propagation Delay Time Sum in to Sum Out t PLH, t PHL = (.7 ns/pf) + ns t PLH, t PHL = (0.66 ns/pf) + 7 ns t PLH, t PHL = (0.5 ns/pf) + 90 ns Sum In to Carry Out t PLH, t PHL = (.7 ns/pf) + 0 ns t PLH, t PHL = (0.66 ns/pf) + ns t PLH, t PHL = (0.5 ns/pf) + 85 ns Carry In to Sum Out t PLH, t PHL = (.7 ns/pf) + 90 ns t PLH, t PHL = (0.66 ns/pf) + ns t PLH, t PHL = (0.5 ns/pf) + 90 ns Carry In to Carry Out t PLH, t PHL = (.7 ns/pf) + 85 ns t PLH, t PHL = (0.66 ns/pf) + 4 ns t PLH, t PHL = (0.5 ns/pf) + 0 ns t PLH, t PHL 5. The formulas given are for the typical characteristics only at 5 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance ns = - V GS V out = V GS V out I OH EXTERNAL POWER SUPPLY I OL EXTERNAL POWER SUPPLY Figure. Typical Source Current Characteristics Test Circuit Figure. Typical Sink Current Characteristics Test Circuit 4

5 0 ns 0 ns V in 90% % V SS PULSE GENERATOR 500 F I DD Figure. Dynamic Power Dissipation Test Circuit and Waveform PULSE GENERATOR I DD 0 ns 0 ns - 90% 50% % 50% t PHL 90% 50% % t PLH t THL V SS t PLH V OH V OL t TLH V OH V OL t PHL Figure 4. Switching Time Test Circuit and Waveforms 5

6 Figure 5. Logic Diagram TYPICAL APPLICATION WORD A + B INPUTS C 4 out SUM OUTPUTS Calculation of bit adder speed: t P total = t P (Sum to Carry) + t P (Carry to Sum) + t P (Carry to Carry) The guaranteed bit adder speed at V, 5 C, = 50 pf is: t p total = = 900 ns Figure 6. Using the MC4008B in a Bit Adder Configuration 6

7 PACKAGE DIMENSIONS A 9 8 B SOIC CASE 75B05 ISSUE K P 8 PL 0.5 (0.0) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 98.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.7 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.7 BSC 0 BSC J K M P R T SEATING PLANE G D PL 0.5 (0.0) M T B S A S K C M R X 45 J F SOLDERING FOOTPRINT 8X 6.40 X. X PITCH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4008B/D

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