Assembly Process for 2.5D TSI Packaging Assembly Team

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Benedict Bates
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1 Assembly Process for 2.5D TSI Packaging Assembly Team Property of Institute of Microelectronics (IME)-Singapore August 17, 2012

2 Outline Technical Challenges of 2.5D TSI Assembly Proposed 2.5D TSI Assembly Process Flow IME Assembly Capabilities and Micro Bump Bonding Roadmap IME Technical Competency in Micro Bump Bonding Process Reliability Test Capabilities at IME Possible Research Outcome 2

3 TSI Assembly Process: Key Technical Challenges Wafer level over molding: warpage issue Optimized wafer level compression molding using new materials Warpage correction methods Underfill for micro bumps New capillary UF with small filler size to achieve void free and min fillet at the die sides Wafer level UF Challenge Approach IC-1 IC-2 Substrate TSI C4 bump Thin wafer handling for C2W Molding tape as carrier Carrierless TSI process Micro bump joining/chip Stacking C2W bonding using Thermal compression C2W bonding using wafer level underfill 3

4 2.5D TSI Assembly Process Flow Mold Tape as Carrier Approach Support wafer Temporally bonding glue 0. TSI Wafer UBM Molding tape Carrier for molding process 1. TSI Wafer De-bonding and mounting on to molding carrier with tape IC-1 IC-2 IC-1 IC-2 Molding tape Carrier for molding process 2. C2W Bonding IC-1 IC-2 IC-1 IC-2 Molding tape Carrier for molding process 3. Underfilling process IC-1 IC-2 Frame IC-1 IC-2 IC-1 IC-2 Frame IC-1 IC-2 5. BGA Ball attachment IC-1 Molding tape Carrier for molding process 4. Wafer Level Molding Dicing Tape IC-1 IC-2 Frame IC-1 IC-2 6. Dicing Frame TSV Interposer PCB IC-2 7. Package Assembly on PCB 4

5 2.5D TSI Assembly Process Flow Carrierless Approach 0. TSI Wafer with front side RDL IC-1 IC-2 IC-1 IC-2 IC-1 IC-2 Frame IC-1 IC-2 6. Backside RDL, BGA Ball attachment 2. C2W Bonding IC-1 IC-2 IC-1 IC-2 3. Underfilling process Frame IC-1 IC-2 IC-1 IC-2 4. Wafer Level Molding Frame IC-1 IC-2 IC-1 IC-2 Dicing Tape IC-1 IC-2 Frame IC-1 IC-2 7. Dicing IC-1 Frame IC-2 TSV Interposer PCB 8. Package Assembly on PCB 5. Via exposer at TSI backside 5

6 IME Advanced Packaging and Assembly Wire Bond Packaging Flip Chip Packaging Wafer Level Packaging 3D IC Packaging Back Grind Dicing / Laser Dicing Die Attach Wire Bond Mold / Encap Back Grind Dicing / Laser Dicing Flip Chip Attach Underfill Reflow RDL UBM Embedded Passives TSV & Si machining Bumping Reliability Testing TSV with double side RDL and bumping Dicing C2C and C2W bonding Wafer level molding Wafer level solder ball attachment Backgrinder with inline mounter Capability: 8 & 12 size wafers Fine Pitch (30μm ) Wire Bonder Cu wire bonding Ultra low loop bonding Wire dia: 0.5 to 1.3mil Wafer level compression mold press Capability: 8 & 12 size wafers Solder Jetter Substrate size: 10mm x 10mm size substrate to 8 & 12 size wafers Solder ball sizes: 40μm to 760μm Flip Chip Bonder Capability: C2C and C2W on 8 & 12 size wafers Chip Size: 0.2 to 40mm accuracy: +/-0.5μm Bonding method: thermocompression and thermo-sonic 6

7 Reliability Testing Capability Test Electrical Follow up Moisture sensitivity testing Electrical test before & after Failure Analysis if required Thermal Cycling to 1000 cycles Electrical test at 0, 200, 500, 750, 1000 cycles Failure Analysis if required High Temperature storage Electrical test at 0, 200, 500, 750, 1000 hours Failure Analysis if required Temperature Humidity and/or un-biased HAST Electrical test at 0, 200, 500, 750, 1000 hours for temperature humidity, before and after for HAST Failure Analysis if required 7

8 Characterization and FA Capabilities Transmission Electron Microscopy (TEM) Dual beam Focused Ion Beam Microscopy (FIB) Auger Electron Spectroscopy (AES) Atomic Force Microscope (AFM) Scanning Acoustic Microscope (SAM) Wafer Level Device Characterization (DC) 8

9 Possible Research Outcome Optimized 2.5D TSI Assembly Process Flow Mold tape as carrier vs Carrierless approaches Micro Bump Bonding Process For C2W Assembly Underfilling Process for Micro Bump Interconnects Evaluation of Capillary UF for micro bumps Evaluation of Wafer level UF Wafer level compression molding for C2W TSI wafer Overmolding New mold compound materials evaluation for TSI over molding Moldable UF material evaluation Reliability Assessment of 2.5D TSI Vehicle 9

10 Technical Challenges: Micro Bump Bonding Open Solder joints due to thin chip warpage Open Solder joints due to thin chip warpage Chip warpage during reflow of flip chip process Chip warpage during reflow of flip chip process Concerns: Chip warpage impacting the micro-bump joining Stress level on TSI wafer during C2W bonding Approaches: Modeling: Chip level, package level and TSI wafer level warpage simulation Assembly Process: Thermal Compression for C2W assembly Wafer level Underfill 10

11 Technical Challenges: Underfilling for Micro Gaps UF Fillet size UF Void UF Void IC-1 TSI C-scan and Thru-scan images of 2.5D package with capillary UF for 100um pitch micro bump interconnections Concerns: Underfill material may not fill up the micro gap between the chips as Gap between the chips is very small (<30µm) Large fillet size at the side of the chip which restricts the closer placement of chips on TSI and will result large TSI size Approaches: Evaluation of new capillary underfill materials with fine filler size Chip to wafer assembly using Wafer level Underfill Evaluation of Moldable Underfill material Schematic of chip on TSI with UF 11

ball placement and singulation Approaches: Modeling and Simulations: Wafer level warpage simulation to predict the process

12 Technical Challenges: Wafer Level Molding Wafer level warpage of the Molded wafer Warpage of the Molded wafer > 3mm Concerns: CTE mismatch between silicon and mold compound resulted in high warpage The warpage may impact subsequent processes such as ball placement and singulation Approaches: Modeling and Simulations: Wafer level warpage simulation to predict the process dependency Molding Process: Selection of suitable mold compound for thin C2W over molding Warpage correction method by thermal treatment 12

13 Thank you Q & A 13

A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages

A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages Bernd K Appelt Director WW Business Development April 24, 2012 Table of Content Definitions Wafer Level