Packaging point of view. What about assembly technology?

Transcription

1 Packaging point of view What about assembly technology? Silicon 17.0 mm Substrate 2.0 mm Pitch= mm SUBSTRATE Conductor Pitch= mm SUBSTRATE Interposers Silicon 3.0 mm Pitch= mm SUBSTRATE Yves Ousten IMS 2008

2 Silicon toward Package Chip on the package Package toward Card Assembly of the package on a card Card Set of electronic cards Card on a card System

3 What is Package - Chip protection :chocks and moisture - Better handling of the component - rigidify the component on the substrate - Maintain the electrical connection of the component within environment DIL SO PGA BGA µbga CSP Flip Chip

4 Size reduction of the PCB (Printing Circuit Board) New way in red More function in the Silicon chip Size reduction of the silicon technology More transistor on the chip More electronic in the human activity But: Do you want all the functions inside a chip and what is the price? 4/59

5 Cost difference between SoC and SiP Purchasers need only the right function and not all the function into a package! One level would be a specific function removable vs application. Plastic packages are more and more need for applications! Ceramic (LTCC) are also in the race. Problems are coming from the CTE mismatch! Humidity is also a possible cause of defect. Source IMAPS US /59

6 Evolution of the packaging SOC is expensive SiP is increasing : POP, PIP, Stack, 3D levels Multilevels But: Yield of a wafer*yield of the uper wafer = lower yield!! 6/59

7 Categories of SiP (ITRS source) This diagram present that many SiP require solder not only at the final stage of the component but also some components have already been solder ball before their integration in the final package. 7/59

8 Evolution of the SiP 8/59

9 Recommended Areas of Focus for IMAPS Members Develop Feasible Embedded Components. Develop Enhanced Materials to Enable Wafer Level Packaging. Bring Solutions to Resolve Thermal Management Issues. Develop New Materials to Reduce System Cost While Delivering the Necessary Performance. Close the Gap Between Chip and Substrate Interconnect Density. Resolve the issues low K and Cu bring to Packaging. Source IMAPS US /59

10 Process: Printing systems (1/2) Solder paste is introduced on the screen printing and a squeegee and the hard rubber push the paste through the mask. Important the viscosity of the solder paste and the grain size of the solder inside the paste. 10/59

11 Process: Printing systems (2/2) By regulating the doctor blade angle and doctor blade speed parameters, sufficient pressure is applied to the solder paste to fill (push the paste through) the THR drill holes. 11/59

12 Process: Pick and Place First the loader with a data matrix code or a barcode to reach the good component. Secondly the speed of the machine flexible and link to component size. 12/59

13 Process: Reflow (1/2) For Lead solder the temperature pick is close to 224 C For lead free solder such as SAC: Sn Ag Cu 305 = 3% of Ag, 0.5% of Cu. Temperature 254 C max (30 C more!!) Time duration of the process: 60 to 120 minutes Number of thermal zones : 5 to 12 Table reflow for labs Width : 3 to 10 m 13/59

14 Process: Reflow (2/2) Max temperature 254 C time duration of the pick 30 to 45S WIRE 14/59

15 Thermal management Designer calculate the thermal evacuation for different levels inside the 3D component. It is why processor are placed at the bottom of the component and sensors at the top level. Generally memories are placed between to levels diffusing heat flow. In place of the silicon carrier copper could be used. 15/59

16 Chip stacking Interposers Silicon 3.0 mm Pitch= mm SUBSTRATE Interposers: to assure the rigidity of the chip The chip is thinner 100 µm (polish) Bonding made with copper wire (15 µm) Substrate between level1 and balls in FLEX technology Pitch of the balls 0.6mm FLEX 16/59

17 Ball Bonding in copper (1/3) From (a) to (d) Ball forming and bonding on the chip From (d) to (g) wedge or stitch bonding from the chip to substrate 17/59

18 Ball Bonding in copper (2/3) Thermosonic Bonding from the chip to the circuit Ultrasonic from the circuit to the outside of the circuit Generally the chip is reported on the die attach and the die on a specific support (tape). This tape is used for the automatic bonding on the final circuit 18/59

19 Ball Bonding in copper (3/3) Wedge bonding Different bonding power with ultrasonic increasing 260mW, 35g, 30ms 370mW, 35g, 30ms. Stitch bonding 19/59

20 Bonders Wedge bonder Ultrasonic only Pressure of the head Ball bonder Ultrasonic Thermal (~150 C) Pressure of the head 20/59

21 CTE between Silicon and interposer Warpage! Interposer = silicon Active chip glue on the interposer The interposer is less long than chip Problem is the warpage Wedge Al 21/59

22 How to manufacture this component? Generally the dies are coming from different wafers. After a test and the sawing of the wafer manufacturer stack the dies. But between the dies an interposer is placed to minimize the strain between dies. Also interposer reduce the warpage 22/59

23 Flip chip and Package on Package (PoP) Silicon 2.0 mm Pitch= mm SUBSTRATE The principal problem for this kind of technology is The balls inside the package The balls outside the package Same material inside and outside! Also warpage between the different levels 23/59

24 Balls The ball is in solder Lead free Thinner Problems: Intermetallics Cracks due to CTE Thermal management Warpage due to length of the component and also its thickness 24/59

25 Balls report on the chip first solder ball is eutectic solder, and a customized stress compensation layer (SCL) material is applied by squeegee printing. Instead of planarization, a hole is developed out of the layer to expose each solder ball. Polymer collars help to extend temperature cycle reliability for FCT's Ultra CSP. (Source: Flip Chip Technologies) 25/59

26 View of balls under the package (PoP) The big problem is the double reflow of the component. The biggest one is the open circuit. Problem of thermal management Bad soldering of the component Copper diffuse on the solder paste during the different reflows. 26/59

27 Balls report on the PCB 27/59

28 Underfill: What is it? The use of the underfill is conditioned to the minimization of the strain during reflow process of the flip chip. It is also used for the protection as barrier for the moisture. But: Thermal constant elasticity must be the same as the solder and the package. Applied the underfill Soldering of the flip chip and underfill polymerization Placed flip chip over the underfill paste Put the flip chip on the pad through the underfill 28/59

29 Package stacked or Package on package Strictly speaking these should be part of a system in package PoP are pretty unique in several ways as shown on the three pictures Figure 3 is used to stack memories such as AMKOR memories. Diameter of the balls for these devices are closed to 0.2 to 0.4 mm. (figure 5) 29/59

30 Balls reduction size 30/59

31 What happens when the size of the balls reduce? Calculation made with analytical software (linear properties) on EURELNET. Analysis of 3 different packages considering solder intermetallic (package 3). Conditions Package 1 Package 2 ( Silicon ) * Package flip chip Length = 6 mm Width = 6 mm Thickness = 260µm CTE= 2.62 ppm/ C Young s Modulus = 160 GPa * Ball (SAC405) Ball Grid Array : 7*7 Pitch = 0.5 mm Diameter = 0.33 mm Height = 0.31 mm Young s Modulus = 45 GPa * Solder (SAC405) Young s Modulus = 45 GPa ( Silicon ) * Package flip chip Length = 6 mm Width = 6 mm Thickness = 260µm CTE= 2.62 ppm/ C Young s Modulus = 160 GPa * Ball (SAC405) Ball Grid Array 13*13 Pitch = 0.25 mm Diameter = mm Height = mm Young s Modulus = 45 GPa * Solder (SAC405) Young s Modulus = 45 GPa Package 3 ( Silicon ) * Package flip chip Length = 6 mm Width = 6 mm Thickness = 260µm CTE= 2.62 ppm/ C Young s Modulus = 160 GPa * Ball (SAC405) Ball Grid Array 13*13 Pitch = 0.25 mm Diameter = mm Height = mm Young s Modulus = 45 GPa * Solder (less elastic SAC405 + intermetallic) Young s Modulus = 55 GPa * PCB CTE = 15 ppm/ C * PCB CTE = 15 ppm/ C * PCB CTE = 15 ppm/ C 31/59

32 Normalized Normalized shearing displacement (NSD) 1 0,8 0,6 0,4 0,2 Results 0 0 0,10,20,30,40,50,60,70,80,9 1 array center Distance r from array center Source EURELNET 2008 NSD N NSD R NSD RI Cu6Sn5 The reduction of the balls scale induced an higher IO density. The criticality of the package assembly increase (in term of strain during the reflow process). The introduction of intermetallic in the solder increases the criticality of the assembly. Cu SAC Source SERMA 2007 Conclusion Limitations of analytical calculations : Creep and non-homogenous structures. But interest to extract information about tendencies 32/59

33 Intermetallics Sn from the molten reacts with Cu in the pad to form intermetallic phases. Cu forms generally two different materials: Cu 3 Sn and Cu 6 Sn 5 Kinetics of the Cu 3 Sn used in the reflow soldering is very slow 150 C 33/59

34 Ball cracks Crack propagation along a Ag 3 Sn phase. Optical micrographs of solder joint cross sections on Cu UBM/Cu pads on organic substrates after thermal cycling 0 to 100 C. Microelectronic packaging, CRC Press /59

35 3D Package Multi Levels 17.0 mm Pitch= mm SUBSTRATE Substrate Conductor Each level is build around a function. Each level would be tested independently. Quality test would be made before packaging. Report on each levels would be mutualized during the process. Passive components embedded in the package. 35/59

36 WLP (wafer level package) Through silicon via (TSV) source NXP interconex 2008 Through silicon via Wafer level package Via close to 100µm Problems : cross talk and crack risk inside silicon. 36/59

37 WLP : Gluing or Soldering? Assembly the chip on the substrate Glue or solder ( S ) Size réduction Nb I/O

38 WLP : From NXP Thinning techniques are used to make thinner the wafer (200µm) 38/59

39 Printing system MCM (1/14) Raclette poussant encre encre Elément photosensible image du motif reporté dessus Epaisseur permet de contrôler l épaisseur du dépôt Substrat

40 MCM (2/14) L écran de sérigraphie est constitué du cadre aluminium rectifié moulé d une toile en fil d acier d une émulsion photo sensible Vue en coupe

41 MCM (3/14) Transfert de l image (TYPON) sur l écran de sérigraphie UV TYPON correspondant à 1 niveau Eau pour révéler les parties non exposées aux UV 1 ECRAN par NIVEAU

42 MCM (4/14) Séchage de l encre à 120 C durant 15 à 20 minutes Epaisseur 40/50µm Epaisseur 25/35µm EVACUATION DES SOLVANTS

43 MCM (5/14) Four à passage IR T C Frittage Table chauffante 850 / minute 405 Time minutes 45 to 75

44 MCM (6/14) Four à passage SORTIE ENTREE

45 MCM (7/14)

46 MCM (7/14) Vue au MEB d une Résistance sérigraphiée

47 l L MCM (8/14) L R =ρ. avecs = l. h S L h l Encres disponibles en pots 10Ω, 100Ω, 1kΩ, 10kΩ, 100kΩ, 1MΩ λ λ λ 250 μm Les résistances sont frittées en commun

48 MCM (9/14) P = 100 mm 0 mw/ P P 0 = S = L* l R = R. o L l 2 l Puissance dissipable par une résistance sérigraphiée Sur une alumine Ro R = Dès que l on dissipe plus l augmente. P P 0 Cette règle permet d éviter les point chauds!

49 Implantation des conducteurs MCM (10/14) En général largeur 250 µm Écart entre deux conducteurs 250µm Faire en sorte qu ils soient pas trop longs Le croisement de conducteurs sur 2 niveaux s effectue perpendiculairement

50 Un VIA MCM (11/14) C est un contact entre Deux niveaux λ = 250µm En général il existe un masque Pour remplir les VIAs Respect de la planéité du support!

51 MCM (12/14) REALISATION CIRCUIT DAO REALISATION TYPONS DES ETAGES OUI SERIGRAPHIE COUCHE N SECHAGE CUISSON RESISTANCES? FIN CREATION DES ECRANS SERIGRAPHIE OUI Autre couche? Ou Autre encre? NON AJUSTAGE RESISTANCE S IL Y A LIEU REPORT COMPOSANTS TESTS ENCAPSULAGE

52 MCM (3/14) AJUSTAGE DES RESISTANCES JET de SABLE < 25µm Ou LASER YAG Réduction de la largeur de la résistanc R = R. o L l l diminue R augmente

53 MCM (14/14) AJUSTAGE DES RESISTANCES Coupe normale par Laser Coupe en L Coupe normale par sablage Coupe multiple par Laser Forte augmentation de R Attention risque de points chau

54 Passive components (1/5) Tantalum capacitor Ceramic capacitor Type 1 or 2 Quartz Resistors (Thick of thin film) Some time carbon resistors Aluminum capacitors 54/59

55 Passive components (2/5) Ceramic capacitors Most known X7R (60% of the panel) Risks are induced by the - Reflow process. PCB bending CTE mismatch 55/59

56 Passive components (3/5) The problem of this technology is the price You need a big mass production to 56/59

57 Passive components (4/5) Embedded components directly inside the PCB (printing circuit board) The technology of the PCB is based on the laminate of different plastic layers. If you provide specific layers based on dielectric to built some capacitors or resistors you make a big gain in term of place and reliability. 57/59

58 Passive components (5/5) Passive components would be embedded on the PCB but: Decoupling capacitors are not really bigs in term of value They are not stables with the temperature Resistance value is not enough high (800Ω/sq) Film adhesion is not good Behavior Versus frequency interesting only up to 2GHz But Why not? Embedded flip chip? 58/59

59 Thank you for your attention! Any questions? Ladybug do you know her? 59/59