A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages

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1 A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages Bernd K Appelt Director WW Business Development April 24, 2012

2 Table of Content Definitions Wafer Level Fan-Out Technology Panel Level Fan-Out Technology Panel Level Embedded Technology Summary 1

3 Emdedded Component Technology WL Fan-out = ewlb = awlp PL Fan-out = aease+ PL embedded = aeasi 2

4 Emdedded Component Technology Ultimate Objective Miniaturization of SiP Die / WLP Passive component Passive component Die Die Die / WLP Passive component Passive component Die / WLP Die Passive component Die Die / WLP Passive component Die Die Die / WLP Passive 3

/ WLP Passive component Passive component Die / WLP Die Passive

5 WL Fan-out = ewlb = awlp Key attributes Wafer Level process environment Low CTE Mold Compound Long term proven process technology ex WL molding Yield > 99% Design optimum when die designed for flip chip Business Model: one stop shop 4

process technology ex WL molding Yield > 99% Design

6 ewlb = awlp Roadmap Technology Item HVM Available Max. Package Size (mm 2 ) 8X8 10X10 11x11 12x12 13X13 Mold / PKG Thickness (mm) 0.49/ / Ball Pitch/Size (mm) 0.5/ / / / RDL Trace Polymer Opening (um) Width/Space (um) Thickness (um) 6.7 um Polymer 20/20 15/15 8/8 6/ Number of RDL Layers >2 -- Min. Die Pad Pitch (um) Min. Die Pad Pass. Opening (um) Multi Die Single die 2 dies 2 dies 5 >2 with discrete passive --

4/0.25 0.3/0.17 0.3/0.15 -- RDL Trace Polymer Opening (um) Width/Space (um) Thickness (um) 6.7 um Polymer 20/20 15/15 8/8 6/6 -- 7.

7 awlp Technology Development Small Die Large Package Thin Package 2D Multi-die 2D Multi-die w/ Passive 3D Double-sided Multi-RDL Fine Pitch Die New Polymer for TC Enhancement 12 awlp 6

8 awlp Technology 2D Multi-die Passed Package & Board Level Testing on Std. structure 2 die 2D package OM in qual phase (Q1 12) Minimum spacing between dies & at die edge are tested at 50 um 8X8 2-Die Test vehicle 50µm Gap between Dies 50µm Mold Perimeter 2D Active Die & embedded SMT Passives One die with SMT capacitor engineering build 0402 & 0201 capacitors are successfully put on Reconstitution wafers 2 die with one IPD engineering build Capable of handling 4 um thick UBM IPD w/o mold flash using Std. adhesive (10 um glue layer), and with thicker adhesive can cover thicker UBM Capacitor Silicon Silicon Capacitor Die placement finished Debonding finished SMT Capacitor & Die 7 IPD & 2 Die

Perimeter 2D Active Die & embedded SMT Passives One die with SMT capacitor engineering build 0402 & 0201 capacitors are successfully put on Reconstitution wafers 2 die with

9 awlp 3D Double Sided Two approaches for 3D awlp are ongoing Through Mold Laser Via High level of mold filler makes clean laser via difficult. Development ongoing for optimum process. Rough sidewall challenges metallization of via. Embedded TSV Die for 3D Feed through Embeds small TSV die in mold compound as a 2D SBS awlp for 3D interconnectivity (Q2 12). 14x14 one die with two TSV die etsv die image TSV hole 8

Rough sidewall challenges metallization of via.

5 mm RDL L/S: (1) 8/8; (2) 10/10; (3) 12/12; (4) 15/15 THB1000 (Q2 12) Current leakages on RDL 8/8 um meet the criterion (I < 10-10 A by 5V

10 awlp Technology MultiLayer RDL Enables RDL layout for high density chips Five RDL designs for evaluation Fine Pitch Die Pads & Lines/Spaces RDL trace line/space (Qualification phase) OM 8/8 SEM 8/8 THB (leakage measure) TV 7.5x7.5 mm RDL L/S: (1) 8/8; (2) 10/10; (3) 12/12; (4) 15/15 THB1000 (Q2 12) Current leakages on RDL 8/8 um meet the criterion (I < A by 5V input) Finer pad pitch and polymer opening Achieved L/S 8/8 um. Testing capability of current process flow and material sets for pad pitches below 50µm & polymer opening achieved 10 um 40 µm Pad pitch 9

11 PL Fan-out = aeasi+ Key attributes Panel Level process environment Low CTE laminate + ABF Cu terminals on die Long term proven process technology ex embedding Design based on flip chip and/or wire bond die Test as module as usual Yield > 90% Business Model: multiple stop shop wafer to substrate mfg to OSAT 10

embedding Design based on flip chip and/or wire bond die Test as module as

12 ASE Fanout Panel Development Panel Fanout ASE is developing a panel process version of fanout packaging Focusing on lower pin count, Higher Power fanout packages Initial Single Die prototypes passed all package & Board level testing 2D 2-Die PFO in development 3D Double sided PFO in concept design phase 30µm Laser Via 11

packages Initial Single Die prototypes passed all package & Board level testing

13 Substrate FO Prototype Builds 8x8 mm package; 3x3x0.15 mm internal chip 196 I/Os; 200 um bump pitch; 400 um ball pitch Structure A Passed standard package level reliability (MSL3+HAST+TCT+HTST) RDL L/S = 20/20 um Solder resist ~18 um Blind via dia. = 70 um Structure B Passed standard Package level reliability Chip Substrate RDL L/S = 20/20 um Prepreg as encapsulation ~160 um 2L substrate (~100 um possible)

level reliability (MSL3+HAST+TCT+HTST) RDL L/S = 20/20 um Solder resist ~18 um Blind via dia.

14 Process Flow Structure A Dielectric Lamination > Vacuum Lamination Via Formation / Desmear > Laser Drill > Roughen Dielectric Surface Patterning Formation > Seed Layer > Photo-Litho > Cu Plating > Stripping/Etching Solder Resist & Surface Finish > Pretreatment > Solder Resist > Exposure > Development > SR Curing > Surface Finish Ball mount & Saw RDL Pattern X-section of Package After Solder Resist

Stripping/Etching Solder Resist & Surface Finish > Pretreatment > Solder Resist > Exposure >

15 Process Flow Structure B Substrate Chip Substrate Chip Substrate Prepreg Bare substrate > Strip format > 2L, 1/2/1, 2/2/2 Chip Placement > Flip chip bonding > Reflow Chip Encapsulation > Prepreg routing > Strips reconstitute into ¼ panel or full panel > Prepreg stacking -> lamination > Route into strip format Strip ¼ panel Chip Substrate 405mm Ball mount & Saw > Ball placement & reflow > Saw into unit 510mm ¼ panel, after prepreg stacking Chip Substrate Prepreg X-section of 1-package

full panel > Prepreg stacking -> lamination > Route into strip format Strip ¼ panel Chip Substrate 405mm Ball mount & Saw

16 2-die Package Package Specification Package size: 8x8 mm Die size: 3.1x3.1 mm x 2 Package THK: 400 um Die THK: 150 um Die I/O: 196 Die pad pitch: 200 um Ball pitch: 400 um L/S: 20/20 um Blind via diameter: 70um Top view of RDL pattern: L/S 20/20um Interconnection of RDL to Chip thru blind via Solder resist opening for ball mount Chip1 Chip2 X-section of 1 package

400 um L/S: 20/20 um Blind via diameter: 70um Top view of RDL pattern: L/S 20/20um

17 2-die aeasi+

18 Double-sided Fan-out Package Technology extension for 3D or multi-die package application Package on Package application Multi-chip or component assemble on package (MCM) Layer1 Layer2 Process Flow Layer3 Core layer Mechanical drill Pattern formation Cu stud formation Adhesive dispensing & die placement Dielectric lamination Blind via formation Pattern formation Solder Resist Ball mount & Saw

Flow Layer3 Core layer Mechanical drill Pattern formation Cu stud formation Adhesive dispensing &

19 Package Quality - Reliability Package Specification Package size: 8x8 mm Die size: 3.1x3.1 mm Package THK: 430 um Die THK: 150 um Die I/O: 196 Die pad pitch: 200 um Ball pitch: 400 um Inspection items: Cosmetic inspection SAT Open/Short Test Reliability condition Lot1 Lot2 Lot3 Pre-condition - T/C cycle: -55 ~ 125, 5X - Baking: 125, 24hrs - MSL3: 30, 60% RH, 192 hrs - Reflow: 260, 3X HAST - 130'C/85%RH, 33.5 psig, 96/192 hrs TCT ~ 125 HTST Passed Passed Passed 500/1000X Passed Passed Passed 1500X Passed , 500/1000 hrs Passed Passed Passed

Open/Short Test Reliability condition Lot1 Lot2 Lot3 Pre-condition - T/C cycle: -55 ~ 125, 5X - Baking: 125, 24hrs - MSL3: 30, 60% RH, 192

20 Package Quality Board Level Reliability Package Specification Package size: 8x8 mm Package THK: 430 um Die THK: 150 um Lead count: 180 Ball pitch: 400 um Inspection items: Cosmetic inspection Open/Short Test Reliability item Condition Result Drop Test Thermal cycle 30 times (JESD22-B111) -40 ~ 125, 500/1000/1500/2000X (JESD22-A104C) Passed Passed

items: Cosmetic inspection Open/Short Test Reliability item Condition Result Drop Test

21 Package Quality Unit Warpage The maximum warpage of fan-out package is around 52 um, convex, at 260 Factor: reflow times, 3x & 6x Test flow: reflow 3 or 6x -> warpage measurement (shadow moire) Package size : 8x8 mm Die Size : 3.1x3.1 mm Package THK : 430 um No solder ball

22 Panel Level Fan-out: Roadmap Die RDL Solder Resist Technology Attributes Standard 2012 Advanced Die I/O pitch, um UBM Surface Finish Solder Ball Cu THK Cu pad, 7um Cu pad, 7um Cu pad, 7um Cu Pad, 5um or Al Pad Pad Dia Die Thickness, um LW/LS, um 25/25 20/20 20/20 15/15 12/12 Via/Land 70/130 60/110 50/80 30/60 30/60 Pad(RDL), um Ball Pitch, mm Ball Pad, um SRO, um SRR, um +/-30 +/-25 +/-20 +/-15 +/-15 OSP, ENIG, ENEPIG Lead-free Carrier Thickness, um Package Thickness, um (no solder ball)

23 PL Fan-out = aeasi Key attributes Panel Level process environment Low CTE laminate Cu terminals on die Long term proven process technology ex embedding Design based on flip chip and/or wire bond die Test as module as usual Yield > 90% Design software for embedding lacking Substrate test of embedded lacking Extended Cycle time Business Model: multiple stop shop wafer to substrate mfg to OSAT 22

25 aeasi Structures - Structure & Feature LGA Type BGA Type Feature Thin package thickness (< 0.4mm) Excellent electrical performance Double side cooling for better thermal performance 24

26 SiP Module - Embedded Die Substrate - Structure & Features Features Yield enhancement by Know good substrate. Prefabricated known good substrate, before die / component embed, substrate inter-connection and out layer build-up process. High density circuit / multiple layer design in base substrate The base substrate manufacture by existing panel type production line. Following component embedding and out layer processing at embedded line. Enable highly integration 3D PKG solution with assembly and SMT technology. 25

27 a-easi

28 a-easi TM MOSFET a-qfn ( ASE TV1) Project Status Run3 Sample Build----Done MOSFET QFN ( ASE TV2) Project Status Run1 Sample Build----Done MOSFET ( ASE TV5) Project Status Run1 Sample Build----Done TV1/TV2/TV5 Reliability Test Schedule

29 (A) Bump Pitch Cu Bump Chip Cu Bump (B) (C) (D) (E) (F) (A) (F) (B) (C) (D) (E) (F)

30 Die Die / WLP a-easi TM PKG Roadmap SiP Module Die Die / WLP Passive component Passive component Die / WLP Passive component Passive component Die / WLP Passive Die Die component Die Die Passive component Die / WLP Passive LGA Type MCM BGA Type

31 Summary Embedded Technology bursting into market Standardization needed awlp aeasi+ - aeasi solutions with distinct resolution and cost profiles ASE can offer one stop shopping for all three soltuions 30

32 Thank You

Dual Integration - Verschmelzung von Wafer und Panel Level Technologien

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