Fraunhofer IZM Berlin

Transcription

1 Fraunhofer IZM Berlin Entwicklungstrends im LED Packaging Dr. Rafael Jordan SIIT

2 Agenda Chip on Board Gluing Soldering Sintering Transient Liquid Phase Bonding/Soldering Junction Temperature Measurements Silicon Interposer

3 LED Packaging Tasks Optics Filling Wire Bond 1 st & 2 nd Level Interconnect Chip Board Phosphor Submount Underfill Power Cooling

5 Development trends in assembly technology Percent Through Hole (TO & DIP) Bare Die (COB) Surface Mount (SO, PLCC, QFP, TAB) Array (Flip Chip, BGA, CSP, Wafer CSP, PGA) D (Stacked, MCM) Source: Waves of electronic packaging ; Amkor (new colors applied to graph, Fraunhofer IZM)

6 Typical LED COB Modules pollin.de lightinthebox.com Source: Waves of electronic packaging ; Amkor (new colors applied to graph, Fraunhofer IZM)

7 Challenges of COB applications compared to SMD Selection of appropriate surface metallization and materials compatible with COB and SMT process steps Selection of process sequence (COB prior SMT or vice versa) Small pad geometries (die bond pad size 200 x 120 µm and smaller) Handling of small dies (down to 200 x 200 µm²) on wafer tape Availability of bare dies Pad routing vs. pad size vs. minimum pitch Surface cleanliness (avoid any possible contamination on surfaces, e.g. fingerprints, cleaning residues, outgassings, flux residues,oxides) Surface topography (no scratches, no brush marks, low roughness Ra < 0.5 µm, no local defects on bonding pads) Lifetime and reliability of silicone encapsulated wire bonds (interaction of loop strength, loop shape, thermal load, vibration load, material selection)

8 GaAs Flip-Chip n-contact p-contact n-gaalas Reflector p-gaalas active area

9 wire for product compatibility, but not essentiell Wireless GaN - Chips Cree DA1000 OSRAM UX:3

11 R th,eff [K/W] Characterization of Thermal Interface Materials R th,int1 R th,tim Rth, eff T Q R th, eff th,int1 th, TIM th,int2 R th, eff R R th,0 R 1 d A bulk R R th,int2 2,5 2,0 Linear function ~ 1-2 W m K 1,5 1,0 TIM ~ 1/slop 0,5 R th0 0, BLT [µm]

12 Challenges for Glued Interfaces Nanotechnologies to improve heat transfer Multi modal particles Polymer fibres & metallic alloy Surface microstructuring Nano sponge interfaces Vertically aligned CNT Nano-scale optimization TIM optimization Surface optimization Nano-scale optimization Increase thermal conductivity Increase thermal conductivity Reduce BLT Reduce interface resistance Increase thermal conductivity Improve phonon transfer

13 Failure Analyses Glued Die Bond Cross Section LED on Leadframe Focus on Diebond

14 I [ma] Failure Analyses by Diode Characteristic 20 F9 pn-junction A11 F1 F3 F7 F8 F9 F ,0 0,5 1,0 1,5 2,0 U [V] Cross Section LED on Leadframe U/I - Characteristics

16 Wetability of LED Dice Supplier B 40 mil (LM) Supplier B 24 mil (LM)

17 Wetability of LED Dice Supplier A old design Supplier A new design

18 Wetability of LED Dice Supplier A new design Supplier A new design

19 AuSn Phase Diagram Au-rich Sn-rich 278 C e C p: h e+l 1 L 1 +Au e 217 C e 1 ~ 60 W m K

20 Copper Based LED on Silicon Substrate Reflow Soldering with AuSn no Activating Atmosphere x-ray x-ray LED-Module 1 x-ray LED-Module 2

21 Copper Based LED on Silicon Substrate Reflow Soldering with AuSn no Activating Atmosphere cross section Cross Section Chip on Silicon

22 Copper Based LED on Silicon Substrate Thermode Soldering with AuSn no Activating Atmosphere x-ray x-ray LED-Module 1 x-ray LED-Module 2

23 Copper Based LED on Silicon Substrate Thermode Soldering with AuSn no Activating Atmosphere cross section Cross Section Chip on Silicon

24 Copper Based LED on Silicon Substrate Thermode Soldering with AuSn no Activating Atmosphere cross section close up look Cross Section Chip on Silicon

25 SnAgCu Phase Diagram ~ 30 W m K

26 Copper Based LED on Silicon Substrate Reflow Soldering with SnAg with Activating Atmosphere x-ray x-ray LED-Module 1 x-ray LED-Module 2

27 Copper Based LED on Silicon Substrate Reflow Soldering with SnAg with Activating Atmosphere cross section Cross Section Chip on Silicon

28 COB assembly LEDs on AlN AlN/Si test board for optical, electrical, and thermal LED characterisation Exsample (rigth): 8 SemiLeds LEDs soldered on AlN with AuSn BMBF-Projekt Nanolux - White LEDs for General Lighting

29 Test Assembly with OSRAM LEDs OSRAM LEDs on AlN Subassembly with wire bonds

30 OSRAM LED Dice on metallized AlN Watercooler 600 W

31 OSRAM LED Dice on metallized AlN Watercooler, 600 W

32 OSRAM LED Dice on metallized AlN Watercooler x-ray

34 Assembly with Ag Sintering Chip to Chip Chip to copper

35 Ag Sintering SEM Pictures Ag-Powder after drying Ag-Powder heat without force Ag-powder heat and force

36 Ag Sintered Interconnects comparing of two suppliers Cross Section with SEM preparation effect AlN Ag Plated Layer Ag Plated Layer Ag Bond Ag Bond Cu supplier A supplier B

37 Ag Sintered Interconnection, FIB Analysis Ag plated well defined interface Ag sintered

38 Ag Sintered Interconnection, FIB Analysis small pores almost disoluted ~ 370 W m K

39 OSRAM LED Dice on metallized AlN Watercooler, 1200 W pressure less sintering

40 Shear Forces for Pressure Less Sintered LEDs Temperature Chip A on Ceramic Chip B on Ceramic Chip A on IMS Chip B on IMS 225 C (8,4 ± 2,1) N (8,8 ± 3,0) N (7,6 ± 3,1) N (7,5 ± 1,5) N 275 C < 0,5 N (8,3 ± 1,9) N < 2,0 N (12,7 ± 2,9) N

41 Pressure Less Sintering pro/contra Standard Equipment (Screen printer + P&P + Reflow) No mechanical fixing of parts during sintering No special atmosphere during sintering Lower Shear forces than sintered/soldered dice Metallization of die bond pad must be suitable Smaller process windows (especially regarding drying)

43 TLPB using electroplated Cu/Sn soldering annealing Si Cu 3 Sn Cu 6 Sn 5 Cu 3 Sn Cu

44 TLPS SAC-paste plus Cu spheres Cu h Cu 6 Sn 5 Sn e Cu 3 Sn 40 wt.-% Cu ( Cu 6 Sn 5 ) 20 wt.-% Cu Pore 40 wt.-% Cu (Cu 6 Sn 5 ) After soldering 40 wt.-% Cu

45 TLPS SAC-paste plus 40 wt.-% Cu spheres Proprietary Process and Paste Si-Chip DAB

46 Thermocompression Bonding with Stud Bumps

47 Thermocompression Bonding with electroplated Bumps

48 Nano - Sponge Potential Application: - low pressure, low temperature bonding (MEMS, laser) - compressible bonding (acommodate topography) - containment for medical applications - large surface area (sensors, catalytics) - bio compatible (e.g. neuronal interface) 13 nm pore size - optical devices (plasmonics, SERS) Flip Chip Sintering bonding zone densified zone 80% pore volume H. Oppermann, M. Hutter, R. Jordan, et al. (Fraunhofer IZM)

50 Critical Value is the Junction Temperature T J?

51 Strom [A] Spannung [V] Measuring Tj with the forward voltage, calibration 0,005 0,004 0,003 0,002 testing range 0,001 0,000 2,4 2,6 2,8 Spannung [V] 2,64 2,63 2,62 2,61 2,60 2,59 2,58 T = -t1 * ln (U/A1) 03B 2,637: T = -1152,913 ln(u/2,66220) 16B 2,620: T = -1398,438 ln(u/2,64008) 19B 2,640: T = -1220,828 ln(u/2,67310) 08B 2,642: T = -1179,331 ln(u/2,66607) 11B 2,634: T = -1423,025 ln(u/2,65662) 2,57 2,56 2,55 2,54 2,53 2,52 2,51 2,50 2,49 2,48 2, Temperatur [ C] The measurement current must be kept small, not to heat the die up, but out of the horizontal area of the UI characteristic, as otherwise the recalculation of the temperature will be imprecise. As Rp and Ri are different for every die, even within one lot, each LED must be calibrated.

52 Spannung [V] Spannung [V] Measurement Interpretation 3,2 2, mA = 2,58783 V = 25,1 C 3,0 2,56 2,8 2,55 2, T [µs] Meßpunkt [Einheit] Even within the realized switching time below 10 µs, a cooling of the LED is visible. Therefore the record transient is fitted with a biexponential curve with offset. The first half-value period is related to the thermal equilibration of the junction with the LED die, the second for the equilibration of the die with the substrate. The offset is simplified sum for the equilibration with the ambient and the final forward voltage at ambient temperature.

53 Voltage [V] Example of a Flat Panel Light Source 2,535 2,530 2,525 2,520 2,515 2,510 2,505 LED@010mA at secundary current = 010mA = 2, V = 24,16 C LED@050mA at secundary current = 050mA = 2, V = 26,44 C LED@080mA at secundary current = 080mA = 2, V = 28,51 C LED@120mA at secundary current = 120mA = 2, V = 31,72 C LED@120mA at secundary current = 080mA = 2, V = 30,08 C LED@150mA at secundary current = 150mA = 2, V = 34,28 C LED@175mA at secundary current = 175mA = 2, V = 36,11 C LED@200mA at secundary current = 200mA = 2, V = 38,66 C LED@225mA at secundary current = 225mA = 2, V = 40,91 C LED@250mA at secundary current = 250mA = 2, V = 43,52 C Time [µs]

54 Thermal comparative study of 1 st Level Interconnect (gluing/soldering/sintering) 1 st Level Interconnect 2 nd Level Interconnect Chip Board Water Cooler Test Szenario: LED auf MC-PCB, MC-PCB auf Kühlkörper, T = 25,0 C I 1 = 100 ma, I 2 = 350 ma, I 3 = 700 ma

55 U [V] Thermal comparative study gluing/soldering/sintering e.g. blue LED glued 2,44 2,42 2,40 I 1 = 100 ma I 2 = 350 ma 2,38 I 3 = 700 ma 2,36 2,34 0,000 0,002 0,004 t [s] sample 1 sample 2 sample 3

56 T [ C] Thermal comparative study: white LED 70,00 65,00 60,00 55,00 50,00 45,00 40,00 'white' glued 35,00 'white' soldered 30,00 'white' sintered 25,00 100,00 300,00 500,00 700,00 900, , , , , ,00 thermal load (optical emission corrected) [mw]

58 Variety of Silicon Approaches V1 V2 V3

59 Thermomechanical Aspect of TSVs Pumping Scallops TSV-Ø 6 µm Through Silicon Via (TSV)

60 Thermal Flow Simulation of TSVs silicon interposer with through silicon vias Si substrate Cu - via Johannes Jaeschke

61 Thermal Simulation of Vias Silikon ausgeblendet Gesamtansicht [ C] Unterseite LED Johannes Jaeschke

62 0,10 mm 4,52 mm 3,52 mm 4,52 mm 0,50 mm Approach for 8 Die Module 1,00 mm 0,16 mm 4,52 mm Si-Board von 100 µm bis 200 µm variieren Polymer oder Si-Rahmen hat eine Dicke von 300 µm

63 Mechanical Analysis for Production Will the thin silicon bottom layer withstand the quick pick & place process during assambly? (force is only applied on the outside ring, no support in the center) Parameter Variations: thickness of bottom layer technique of solder paste application applied force Modell 1 Modell 2 Johannes Jaeschke

64 Mechanical Modell (vertical deformation not to scale) (DP37) Si-thickness: 100 µm diameter: 3000 µm Eq. stress Eq. stress (DPcurrent) Si-thhickness: 100 µm diameter: 50 µm Total deformation Total deformation Si-tickness: 100 µm Si-thickness: 200 µm Johannes Jaeschke

65 0,20 mm 0,40 mm 0,10 mm 2,50 mm 2,90 mm 0,20 mm 0,40 mm 2,10 mm 2,90 mm 1,00 mm Adapted Design 1,00 mm 0,10 mm 0,10 mm 0,20 mm TOP 2,10 mm 3,50 mm 0,40 mm 0,10 mm Bottom 2,30 mm 3,50 mm

66 LED Bulb Simulation Heat sink Silicon-oil Air Helium

67 LED Bulb Simulation