Electroplating aspects in 3D IC Technology

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1 Electroplating aspects in 3D IC Technology Dr. A. Uhlig Atotech Deutschland GmbH Semiconductor R&D Sematech Workshop San Diego/Ca

2 3D Advanced Packaging Miniaturization in size and weight Integration of heterogeneous technologies and complex multi-chip systems Short vertical interconnects Reduced power consumption and parasitics Increased performance and functionality Packaging stacking (PoP, PiP) Die stacking (SiP) (wire bonding & FC) 3D integration with TSVs (W2W, C2W, C2C) 2 Sematech Workshop San Diego/Ca

3 3D Chip stacking Proposed Applications IME ECTC 2008 IBM ECTC 2008 SFT ECTC 2008 Application determines TSV size; type of interconnection, handling sequence, 3 Sematech Workshop San Diego/Ca

4 3D plating applications & Outline TSV Conductive paste printing 50 < d < 100µm Copper plating 1 < d < 70 µm CVD W, poly Si 0,1 < d < 1µm Bumping Cu-RDL/Screen printed solder paste 150 µ < pitch < 400µm Copper pillar/e-plated bumbs 30 µm < pitch < 100 µm E-plated microbumps 10 µm < pitch < 30 µm Metal to Metal pitch < 20 µm Conductive adhesive Sputtering (also C4NP) 10 µm < pitch < 100 µm RDL Al PVD Copper electroplating plating TSV seed layer Sputtered Cu, W, ; CVD; ALD E grafting E less copper 4 Sematech Workshop San Diego/Ca

5 Copper TSV conformal/ bottom up plating status 5

6 TSV plating principles conformal bottom up Drilling/ etching Drilling/ etching Barrier Barrier/ Seedlayer Attach to conductive Support wafer Copper plating/ CMP Copper Plating Wafer thinning CMP/detach both TSV plating technologies will be applied? 6 Sematech Workshop San Diego/Ca

7 Galvanic plating principles Panel-plating Through-mask-plating Barrier & plating base deposition Photo-resist coating & structuring Galvanic deposition Galvanic deposition conformal TSV; DD bottom up TSV; RDL; Pillar Not one plating solution for both technologies 7 Sematech Workshop San Diego/Ca

8 Copper Electrolyte Composition Copper Sulphate g/l Sulphuric Acid g/l Chloride g/l Brightener adsorbs on Copper disables Cu-deposition Carrier desorbs Brightener enables Cu-deposition Leveller adsorbs on copper surpress Cu-deposition Microscopic level Macroscopic level Additives determine deposition quality 8 Sematech Workshop San Diego/Ca

9 Bottom Up TSV electroplating: Status Dimensions 20 x 500 µm 200 x 450 µm Done in collaboration deposition speed not jet optimized 9 Sematech Workshop San Diego/Ca

10 Copper Pillar: Spherolyte Leveller UF Profile uniformity 1 µm/min 2 µm/min 2.5 µm/min 80 µm array bump Profile 4,4 % 4,4 % 6,3 % uniformity - Pillar plating know how to be adopted to very high A/R - TSV related targets? - dimensions, deposition speed (CoO); profile homogenity,.. 10 Sematech Workshop San Diego/Ca

11 TSV Copper plating targets & main impact factors Plating targets 1 void free filling 2 fast 3 low overburden 4 low dimple 5 low stress 5 low additive consumption Main impacting factors Electrolyte/ Additives Current profile Flow (equipment) Via shape Seed layer resistivity 1 Risk of pinch off Avoiding pinch off enables faster void free filling 11 Sematech Workshop San Diego/Ca

12 Role of Additives for pinch off: Leveler Electrolyte Concentration Spherolyte Leveller AT = 10 ml/l TSV Leveler Concentration Spherolyte Leveller AT = 20 ml/l δ N Copper electrolyte Leveller: - strong Copper plating inhibitor - diffusion controlled enrichment Leveler inhibits copper deposition at via aperture preventing pinch off Not one recipe for all TSV dimensions 12 Sematech Workshop San Diego/Ca

13 Role of Current schema: DC versus AC Reverse Pulse current DC AC 1 Cu e - Cu 2 Cu Cu e time TSV Same Electrolyte/ plating time Pulse reverse prevents pinch off & reduce overburden Roughness impact for CMP? 13 Sematech Workshop San Diego/Ca

14 Conformal TSV electroplating: Status Electrolytic copper filling of through silicon vias in different aspect ratio Aspect Ratio 8 Investigated on different seed layer types 5 2 Diameter [µm] 10 µm 20 µm A/R: wide range fillable Speed: 10 x 65 µm in 45 Semitool CFD3 40 µm TSV: initial target (void free ; < 1h) ; target reinforcement required 14 Sematech Workshop San Diego/Ca

15 Atotech s Fe 2/3+ system c(me z+ ) Electrode Electrolyte c 0 (Fe 3+ ) c S (Fe 3+ ) x = 0 x *= 0 δ N Distance x Bottom of TSV: Cu + + e - Cu Top of TSV: Cu + + e - Cu Fe 3+ + e - Fe 2+ 2Fe Cu 2Fe 2+ +Cu 2+ - Fe 3+ : reduces overburden - Hardware & electrolyte modification required - Does a shorter CMP time justify this? 15 Sematech Workshop San Diego/Ca

16 16 Bumping

17 Assembly for 3D Adhesive Solder Metal-to-Metal Electroplated 10 < d < 100µm Printed 100 < d <400µm Evaporated 5 < d < 20µm Microbumping Sn on copper SnAu CoSn Pillar... Bumping SnAg SnAgAu Sn SnPb.. Various suggestions but already consensus? 17 Sematech Workshop San Diego/Ca

18 Micro bumbs - Grain size Pure Tin/ SnAg 3% grain size comparison Tin 221 C SnAg 3% After deposition (40 µm pads) After reflow 235 C Tin (10 µm/min) on < 5 µm TSV to large grain size 18 Sematech Workshop San Diego/Ca

19 Micro bumps - Assembly Geometrical aspects 2,5 µm reflow 5 µm Impact of Wafer bow? 5 µm reflow Risk of Electrical shorts 5 µm micro bumbs W2W? 19 Sematech Workshop San Diego/Ca

20 Microbumps - Reliability Solder joint reliability for fine pitch Source: Eric Beyne IMEC Source: Kim ECTC 2008 Source: Kim ECTC Sematech Workshop San Diego/Ca C 150 C; 5x10 4 A/cm 2 IMC consumes solder (CuSnCu): EM might lead to spalling Sn-Oxid Microvoids

21 Alternatives: Pillar/ RDL Electromigration: reduce local current density Pillar + e-plated solder Tin Copper Redistribution + printed solder 500 µm Kirkendahl voids: Under Bump Metallisation Galvanic Ni/Pd UBM E less Ni/Pd UBM (Cu, Ni, Pd) 6 Sn 5 Ni(P) Source: Lai (ASE) ECTC 2008 Source: Atotech Peaks Sematech Workshop San Diego/Ca

22 Copper Pillar Status galvanic UBM/ Tin 22

23 Copper/Tin Pillar Cu(Ni-P)Sn Pillar 10µm Sn 2µm Ni-P 30µm Cu 50x80 µm copper pillar/ 20 µm Sn; 80 µm pitch Source: IME Singapore using Atotech chemistry Cross section of Cu/Ni/Sn Pillar Source: Atotech Reliability data for Cu/(Ni-P)/Sn microbumps? Thickness, P-content etc Target costs? process time? Plating through photo resist? 23 Sematech Workshop San Diego/Ca

24 Copper RDL + solder paste Status RDL e lessubm Ni/Pd solder & bond reliability Equipment solutions 24

25 Cu-RDL: Spherolyte Leveller UF Within dye uniformity Roughness < 7 nm Deposition rate µm/min 0.6 µm/min 0.8 µm/min 1.0 µm/min Matured process with high within wafer thickness homogenity 25 Sematech Workshop San Diego/Ca

26 E less UBM for soldering Ni(P)/Pd process flow Cu pad: Etch Activator Postdip Ni Pd E less versus PVD E less Metal Pad Sur. Pretreatment Metal dep. PVD Metal Pad PR process Metal dep. PR strip Process on Cu (d >50 µm) pads industrialized E less = mask less process cost advantage 26 Sematech Workshop San Diego/Ca

27 E less Ni/Pd UBM: Soldering Solder Mechanism: IMC Ni/Pd Shear strength: multiple reflow test 1x RF (Cu, Ni, Pd) 6 Sn 5 Ni(P) 3um Ni/0,1umPd/30nm Au 3um Ni/0,1umPd x RF 20 Required minimum strength 3 g/mil 2 (Cu, Ni,Pd) 6 Sn 5 Ni(P) ( Ni, Cu) 3 Sn Number of Reflow Cycle Lot s of experience available (Flip chip) Solder Shear fore: 10x RF; 1000h HAST passed Solder Ball Shear Force [g] 27 Sematech Workshop San Diego/Ca

28 E less Ni/Pd UBM: Wire Bonding Bond mechanism Au Shear strength: HAST Pd 55,0 50,0 0.3 umpd / 3 umni 300nm Ni SEM EDS after 150 C Au Ball Shear Force [g] 45,0 40,0 35,0 30,0 25,0 20,0 15,0 10,0 5,0 Required minimum strength 0,0 0 hr 250 hrs 500 hrs 1000 hrs 150C Shear force within spec 28 Sematech Workshop San Diego/Ca

29 Single wafer immersion & Batch spray tool Semitool Raider Cintillio Single wafer tool Batch tool 10 Wafer/h 100 Wafer/h Commercialized Atotech/ Germany Tools available for low/ high through put front side/ front & back side deposition 29 Sematech Workshop San Diego/Ca

30 Galvanic plating principles conformal plating through mask plating 30

31 Galvanic plating principles Panel-plating Through-mask-plating Barrier & plating base deposition Photo-resist coating & structuring Galvanic deposition Galvanic deposition conformal TSV; DD RDL; Pillar; bottom up TSV 31 Sematech Workshop San Diego/Ca

32 Copper Electrolyte Composition Atotech Additive conformal bottom up Spherolyte Brightener Leveller B Leveller AT 10 x 60 µm 40 x 50 µm Spherolyte Brightener Leveller UF 60 x 70 µm 32 Sematech Workshop San Diego/Ca Electrolyte TSV TSV/Pillar = RDL

33 Copper Electrolyte Composition Copper plating of TSV and RDL will require different Chemistry not at the same plater 33 Sematech Workshop San Diego/Ca

34 TSV Seed layer Requirements e less deposition 34

35 Seed layer for TSV Cu filling depth [µm] Effect of inhomogene seed layer Effect of inhomogene seed layer Seed layer target on wafer: d > 200 nm for good within wafer homogenity inside TSV continuous thickness target tbd (plating speed: the thicker the faster) wettable adhesion to barrier layer TSV diameter µm] IZM/Atotech ECTC 2008 PVD/ CVD show steep learning curve 35 Sematech Workshop San Diego/Ca

36 Electroless copper seed layer E less in Barrier materials: very early stage results 40/40um Electroless copper on Photoresist (+ galvanic copper) 35 x 100 µm Electroless copper on SiON Feasibility of barrier/ seed layer long way to go Is there really a PVD limitation? Relevant TSV dimensions? Road map harmonisation appreciated! 36 Sematech Workshop San Diego/Ca

37 Summary Atotech fully supports TSV direct collaboration with semiconductor industry 200/300 mm plater for e less & galvanic processes in Berlin/ Germany plating for semiconductor dedicated R&D team participation in related academic/ industrial consortia understand needs; performance feed back Copper TSV initial target (void free ; < 1h) target reinforcement required e.g. within wafer distribution, overburden, stress, < 30 min, CTE, CoO high quality/quantity TSV wafer supply is a must discussion about Atotech s Fe 2/3+ process to reduce Cu-overburden Bumping matured technology pieces available, but need to define 3D technology chain 3D stacking dedicated performance to be investigated reliability: academic consortia; cost target: industry e less seed/ barrier infant status required: target definition, wafer supply, how to evaluate, SC industry: road map 37 Sematech Workshop San Diego/Ca

38 Thank you for your attention 38 Sematech Workshop San Diego/Ca