Development of a Design & Manufacturing Environment for Reliable and Cost-Effective PCB Embedding Technology

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Eugenia Turner
9 years ago
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1 Development of a Design & Manufacturing Environment for Reliable and Cost-Effective PCB Embedding Technology

2 Outline Introduction CAD design tools for embedded components Thermo mechanical design rules The industrialisation of chip embedding Outlook and business

3 Development of chip embedding technology

4 Miniaturization Approaches Technology drivers that create large pin count devices SoC more functional density SiP mixed technologies with memory Miniaturization approaches used on PCB systems Mezzanine boards Rigid Flex circuits High Density Interconnect Shrinking pin pitch (< 0.4mm) Large pin count devices Embedded Passives Low pin Actives 2G / 3G / 2 MP GPS / WiFi Memory Slim 3G / 3.2-MP GPS / WiFi More Memory Slimmer profile Battery life

Flex circuits High Density Interconnect Shrinking pin pitch (< 0.

PCB / IC-Packaging design tool requirements 1) Component, layer stack selections Engineers specify Components to be embedded Embed Required (Hard) or Embed Optional (Soft)

5 PCB / IC-Packaging design tool requirements 1) Component, layer stack selections Engineers specify Components to be embedded Embed Required (Hard) or Embed Optional (Soft) Ensures only qualified components get embedded Layers to be used Chip up Chip Down Embedding concept Chip-up, Chip-down Face-up, Face-down Direct (SMD), Indirect (embedded)

(Soft) Ensures only qualified components get embedded Layers to be used Chip up Chip

6 PCB / IC-Packaging design tool requirements 2) Design Rule Checks Component to Component / Cavity Height checks gap between component in cavity to adjacent metal layer Max cavity area Max number of components in cavity Vias within cavity area Metal to cavity area Extended cavity support based on component height etc

metal layer Max cavity area Max number of components in cavity Vias within

7 PCB / IC-Packaging design tool requirements 3) Cavity Support Package driven Keep-out properties User Defined Cavities Manually created Span multiple layers Merge capability Design Rule Checks Max cavity area Max comps within cavity Open Cavity Closed Cavity

Manually created Span multiple layers Merge capability Design

PCB / IC-Packaging design tool requirements 4) Constraint-Driven Place & Route, Mfg outputs Constraint driven place and route Move components to inner layers Don t put a via through the component!

8 PCB / IC-Packaging design tool requirements 4) Constraint-Driven Place & Route, Mfg outputs Constraint driven place and route Move components to inner layers Don t put a via through the component! Route to embedded components adhering to electrical, physical and manufacturing constraints Manufacturing outputs for layers with embedded devices ODB++ etc Dynamic Design for Assembly guided placement

9 Checklist for EDA ECP Capability Supported Planned Workaround Cadence Version: Allegro Beta 16.4 HERMES Support Partner: THALES Functionality for ECP Release: Planned Q2, 2011 ECP component placement between copper layers ECP component pads available for via interconnect ECP component with pads on top and bottom side Possibility to flip and/or rotate each ECP component separately Component span over several copper layers Additional layers for ECP - assembly, glue spots, cavities Separate assembly output for ECP components ODB++ support for ECP Gerber/Excellon support for ECP Via-in-pad technology Filled/stacked via support for sequential buildup

interconnect ECP component with pads on top and bottom side Possibility to flip and/or rotate each ECP component separately Component span over several copper

10 Thermo-Mechanical Assessment Methodology Modelling of stress & strain in embedded structures FEA analysis Failure mechanism Strain distribution Torsion test with strain measurement Design rules

11 Test Vehicle Overview Various 4-6 layer PCBs embedding daisy-chain dies Total thickness : 0.8mm 1.6mm 2.0mm 2 halogen-free base materials Embedded die Embedded gage

12 Daisy-Chain Embedded Dies Thinned down to 150µm, Cu pad plating (FCI) 3 sizes : 3x3, 5x5, 10x10mm² Up to 400 pads/microvia connections Peripheral & full array configurations Pad size : 270µm, 0.5mm pitch

13 Torsion Testing Strain gage measurements under repeated torsion cycles Angle : -7 / +7 Temperature : up to 100 C Assembled Strain Gages Embedded Strain Gages

14 Findings h

15 Sensitivity Analysis Incidence of various design parameters on strain for embedded components Design Parameter PCB Base Material Resin content Conditions Material A vs Material B Halogen-free, high performance FR vs 2116 pre-preg type Results Material A better 2116 better PCB thickness 0.8mm vs 2.0mm Higher thickness better Embedded core thickness Interaction between embedded and assembled components 0.2mm vs 0.4mm Overlap vs No overlap 0.4mm better for thin boards (<1mm) No significant effect for thicker boards Increased strain on Si dies with overlapping

better PCB thickness 0.8mm vs 2.0mm Higher thickness better Embedded core thickness Interaction between embedded and assembled components 0.

16 Process Flow Embedded Core Laser- Drilling of fiducials + overlay Component Printing of Adhesive Assembly of Components Metallizing Imaging Copper plating Lay up & Pressing Drilling of Vias Stripping/Etching 100 % Automatic Optical Inspection Mechanical- Drilling Desmearing

Imaging Copper plating Lay up & Pressing Drilling of Vias

17 Adhesive Printing Control of feature size, shape and volume By novel 3D scanner for large panels determines the thickness and uniformity of the dielectric

18 Component Assembly Optical alignment of Flip Chip component Requires high resolution cameras Pattern recognition of pad design Design Pad diameter: 150 µm Minimum pitch : 200 µm Chip size : 7 x 7 mm

Pattern recognition of pad design Design Pad

19 Component Assembly Siemens X2 machine has two assembly heads 20 nozzle head - twin head For high throughput - for high accuracy

20 Component Assembly Component placement accuracy 20 Nozzle head - twin head 20 Nozzle head Twin head Max. speed comp/h 3700 comp/h Accuracy specified +/- 55 µm, +/- 0,7 +/- 30 µm, +/- 0,07 Accuracy measured +/- 20 µm, +/- 0,035 +/- 11 µm, +/- 0,025

speed 20000 comp/h 3700 comp/h Accuracy specified +/- 55 µm,

21 25 µm technology Exposure with LDI registration fiducial to pattern

22 25 µm technology Exposure with LDI registration front to back

23 25 µm technology Semi-additive technology single board plater Individual control of parameters of each panel Handling of thin cores Unique flow system Pulse plating for via filling Full traceability of process data Single piece flow for improved Flexibility Risk management

24 25 µm technology Final line width Copper thickness

25 25 µm technology Design of motor management module

26 Outlook for embedded modules Industrialization Roadmap

27 Embedding Business TAM = Total Available Market for Embedded Components SAM = Served Available Market

28 Thank you for your attention For more information, go to our Hermes website

Development of a Design & Manufacturing Environment for Reliable and Cost- Effective PCB Embedding Technology

Development of a Design & Manufacturing Environment for Reliable and Cost- Effective PCB Embedding Technology M. Brizoux, A. Grivon, W. C. Maia Filho, Thales Corporate Services Meudon-la-Forêt, France