Wafer Level Fan-out and Embedded Technology for Potable/Wearable/IoT Devices. Max Lu, Deputy Director, SPIL
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1 Wafer Level Fan-out and Embedded Technology for Potable/Wearable/IoT Devices Max Lu, Deputy Director, SPIL
2 2 Outline Market Trend & Industry Benchmark KEY Innovative Package Solutions Molded WLCSP Fan-Out WLP NTI (No TSV interconnection) Enabling Technology for Wearable Devices Summary
3 Electronic Product Market Trend (CAGR) Source: Gartner 2015/06, IDC, IEK CAGR: Compound Annual Growth Rate NB (140, 110, -6.0%) HDD (564, 519, -2.1%) DVD (68, 56, -4.7%) 2018 Volume(M)Unit 6,000 ~ PC (132, 116, -3.2%) Gaming (46, 40, -3.4%) Smartphone (1,275, 2,008, 12.0%) Tablet (264, 278, 1.3%) STB (241, 352, 9.9%) TV (209, 246, 4.2%) Automotive Infotainment (172, 223, 6.8%) Network Infra (10, 12, 2.7%) CAGR(%) IoT (1,100, 5,570, 50.0%) Wearable Device (26, 140, 51.8%) ~ End Product CAGR% Major Product Category PKG Requirement Feature IoT/Wearable Device SMART Phone/ Tablet 50.0%/ 51.8% 12.0%/ 1.3% Connectivity (WiFi, BT, NFC,.. ) MCU/ Memory/ Sensor/ PMIC AP & BB / LP Memory Connectivity/ PMIC/ Finger Print Networking 2.7% ASIC Controller / OI Small Form & Ultra Thin PKG High Bandwidth I/O Small Form & Thin PKG High Bandwidth I/O (Large PKG Size) & High Thermal Automotive 6.8% Infotainment / Entertainment High Reliability & Maturity PKG 60
4 Demand of Wafer Level Package
5 5 Outline Market Trend & Industry Benchmark KEY Innovative Package Solutions Molded WLCSP Fan-Out WLP NTI (No TSV interconnection) Enabling Technology for Wearable Devices Summary
6 Key Innovative Package Solutions Fan-Out WLP NTI (No TSV interposer) Molded WLCSP Die Mold Compound Solder Ball
7 7 Fan-Out WLP NTI (No TSV interposer) Molded WLCSP Die Mold Compound Solder Ball
8 Background of WLCSP Dicing Defect Mode 8 Blade Saw found sidewall crack Sidewall crack check by FIB
9 New Idea Solution for WLCSP SWC Prevention 9 1 Stealth dicing Die Mold Compound Solder Ball Wafer From Molding WLCSP 4 2 Dicing Before Laser? FOWLP (SD) 5 3 Plasma Etching Process Enhancement New Idea!!?? FC-MISBGA New PKG Solution 6
10 10 mwlcsp (Molded WLCSP) Technology Top view Side view Die Mold Compound Solder Ball Merits of mwlcsp (Molded WLCSP) - Solution for 5S/6S protection on WLCSP devices. - Utilize wafer sort to screen out potential issue unit. - Potential board level reliability enhancement.
11 11 Fan-Out WLP NTI (No TSV interposer) Molded WLCSP Die Mold Compound Solder Ball
12 12 Fan-Out WLP Technology Application: Keep sufficient area for PCB board I/O as the die size shrinking (28/20/16nm), application for Mobile AP/ Baseband/ PMIC and HDD/SSD Controller. MCM-FOWLP 2sides RDL FO-PoP Benefit: Small form factor & thinner package (substrate-less). High IO/High bandwidth with fine line/multi-layer RDL routiability. (Line/Space = <10um, >2L RDL layer) FO- WLP = Recon. + RDL + Assembl y D/S 1.Temporary adhesive 2. D/B 3. Encapsulation 4. Carrier/ De-carrier NEW Equipment Demanding : Carrier taping/de taping NEW Material Demanding : Carrier Adhesive/Release Film; Dialectric Polymer; Compound
13 Performance Extreme Slim PoP Approach FO-PoP (3L+1L) Thin PKG FO-PoP (3L+1L) MCM-FOWLP (>2L) <1.0 (mm) Bare Die PoP epop L/S=15/15 L/S=5/5~10/10 L/S=2/2 & 3/3 1.2~1.5 (mm) 2013 BD-PoP/ epop EPS/ ETS Coreless L/S=15/15um PKG Height >1.0mm 0.5/0.4/0.27mm TBP PoP(3D Stacking) 3L(Bot)+1L(Top) RDL L/S=5/5um~10/10um PKG Height<1.0mm High Bandwidth MCM/MCM-PoP 3L(Bot)+1L(Top) RDL L/S=2/2um PKG Height<1.0mm LCI Alternative
14 Key Enabling Technology 14 Through PKG Via Formation 300mm Mold Capability Land Side Capacitor PSV1 Opening Multi-layer Double Sides RDL (2L Bot.+ 1L Top) Fine Line RDL (L/S <10um) All key enabling technologies been well established
15 15 Fan-Out WLP NTI (No TSV interposer) Molded WLCSP Die Mold Compound Solder Ball
16 NTI Stacking Platform Evolution DIC NTI w/ Substrate NTI Substrate less No TSV Interposer No Substrate Die Die Molded Die Die Die Metal TSV Source: Xilinx Silicon Remove / Contact Open Merits of NTI (No TSV Interconnection) Platform - Shortening interconnection distance than traditional TSV interposer. - Reducing interposer process cost without TSV related process cost. - Processing by all exiting MEoL/BEoL equipments.
17 Key Enabling Technology 17 RDL Si Removal Wafer Molding Micro Bump Carrier Bond/de-bond Die Bonding Stealth Dicing Wafer Thinning All key enabling technologies been well developed in the world.
18 NTI Approach Demonstration Result 18 A B C A B C Front side metal layer Foundry (no TSV) Successful demonstrated NTI structure BS C4-bump to FS Metal contacting.
19 Outline 19 Market Trend & Industry Benchmark KEY Innovative Package Solutions Molded WLCSP Fan-Out WLP NTI (No TSV interconnection) Enabling Technology for Wearable Devices Summary
20 Innovative PKG Technology for Wearable Embedded Die SBT Small PKG Size/Height Die on CAP Small PKG Size Two side PKG High Yield / High Integration Active Antenna in SiP Small PKG Size IPD on Die (F2F) Better Electrical Performance Partition EMI Small Form Factor/ High Integration Embedded Inductor Lower PKG Z Ht / Lower Power Consumption Low EMI Noise
21 Outline 21 Market Trend & Industry Benchmark KEY Innovative Package Solutions Molded WLCSP Fan-Out WLP NTI (No TSV interconnection) Enabling Technology for Wearable Devices Summary
22 22 Summary Applications: Smart Phone Tablet Wearable IoT Packaging Solutions: Die Mold Compound Solder Ball Molded WLCSP Fan-Out NTI (No TSV interconnection)
23 Thanks for your attention!!
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