SiP Solutions for IoT / Wearables. Pin-Chiang Chang, Deputy Manager, SPIL
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1 SiP Solutions for IoT / Wearables Pin-Chiang Chang, Deputy Manager, SPIL
2 Electronic Products Integration Trend Year ~ Main Stream Products PC / Notebook Mobile Phone / Tablet IoT / Wearables Market Features Integration Trends Feature : Standard Platform, High Volume Customer : Brand Name OEMs Feature: High Matrix, Low Volume Customer : Many new customers in various application market SoC / PCBA SoC / SiP SiP / PCBA / SoC SiP Opportunity Camera, Finger Print, Wireless Connectivity Sensor Related SiP (Camera, Finger Print) Analog Based SiP (Connectivity, Analog, PMIC, PA/LNA) Wireless Connectivity, PMIC, Sensor Remark SoC plays major role on function integration SiP is only adopted in high end smart phone. Modulize is a trend and SiP plays more important role in this high matrix market
3 SiP Market Overview 6000 Mpcs PMIC Analog SiP Finger Printer Connectivity Camera NB Mobile Phones & Tablets. IoT & Wearable NB Mobile Phones & Tablets. IoT & Wearable NB Mobile Phones & Tablets. IoT & Wearable NB Mobile Phones & Tablets. IoT & Wearable NB Mobile Phones & Tablets. IoT & Wearable SiP Applications : NB application moves in saturation stage. Mobile phones & Tablets is still in growing phase IoT & Wearables is in the beginning of growth. Source: Gartner, Morgan Stanley, SPIL estimation
4 Typical Wearable Device Function Block 1. MCU: Micro Controller, usually ARM base, MCU instead of AP 2. Sensors: Temp, Vibration, Gyroscope, Moisture, Pressure, Altitude 3. Power Management: High integration on Active + Passives 4. Memory: Flash, NVM, SRAM 5. Wireless, Connectivity: WiFi, BLE IC / SiP Design Requirement for IoT market: => Low Cost + Great Performance + Low Power + Easy design-in = Low Entry Barrier
5 Challenge & Key Success Factors In 2017, 50% of IoT and wearable devices will be provided from start up companies built within 3 Years IoT / Wearable Devices Market Features: - Non-Standard Products customers need high integration solutions - Various Start up Players customers don t have much resource on too complicated system design - More Sensitive on Cost, Size, Power and especially time to market Key Success Factors of SiP Solutions for IoT / Wearables: - Provide Total Solution (IC Package + System Level Assembly) - System Design and Testing Capability - High integration and miniaturization solutions 1) EMI Shielding on Package 2) 3D / Embedded PKG Structure 3) Antenna in Package - Gartner
6 Total Solution : Direct Package to SiP Footprint arrangement. RDL. Bump mask design Characterization Reliability validation Chip/ Package Design Wafer Bumping Wafer Sort FOC/ Repsv/ RDL WLCSP Probe card design Test program optimization Drop Ship SiP Module & Package Co-Design SiP Module Design Module Assembly System Level Design Schematic/layout design Package/process design Test System Setup Socket / change EVB design Test program Development Function Test SMT D/W Bond Molding EMI Coating
7 Design Simulation for Wearables Simulation Thermal Stress Electrical Critical Thermal Temperature Contour Flotherm ANSYS Max. Warpage Solder Fatigue Life Mold Flow ANSYS LS-DYNA S Parameter Signal/Power Integrity EMI Simulation Antenna Simulation HFSS, Power SI HSPICE, ADS Q3D, TPA 11a/b/g/n MIMO + BT4.0 SiP Module 11b/g + BT SiP Module EMI, Antenna
8 SiP Key Process Development Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SiP Process Development EMI Coating Embedded Solution Antenna in Package LGA/BGA Package Stack Die on Passives Elevated Inverted F Antenna EMI Coating w/ Partition SiP w/ Embedded Inductor Package w/ Antenna & EMI Shielding LF EMI Solution SiP w/ Embedded Die & Inductor (Under Review) Directional Antenna for NFC
9 EMI Coating & SE Measurement / Simulation Sputter Coating Equipment EMI Scan SE(dB) Frequency (Hz) Coating Thickness Measurement SE (Shielding Effectiveness) Measurement Result SE Simulation vs. Measurement
10 3D SiP Structure 1. Embedded Die in Substrate 2. Work with sub. Vendor to embedded die in substrate 3. Pros : 4. Cons (1) Size & Thickness reduction (2) Better electrical and thermal performance (1) Higher cost (2) Long substrate lead time 1. Stack Die on Passives 2. The seating plane for the top die is made of various height passives with epoxy film. 3. Pros : 4. Cons (1) Size reduction (2) Low cost (1) Thickness (2) Thermal dissipation 1. Dual Side w/ Cavity Structure 2. Use 2L Interposer substrate to form cavity structure 3. Pros : 4. Cons (1) Size reduction (2) High component density (1) Thickness (2) Thermal dissipation
11 Stack Die on Passives SMT (Passives Attach) D/B & W/B MD Singulation Total Height : 0.70mm C Substrate Thickness 0.136mm D Die Thickness 125um F1 Film Thickness after Die stacked 45um±10um H Passives Thickness (01005) R C or L 0.13 ± 0.02 mm 0.20 ± 0.02 mm
12 Embedded Inductor ~1.3mm 0.9mm Original SiP Module - Substrate : 2L - Package Height: 1.3mm Discrete Inductor - Size: 2 x 1.6 x 1.0 mm - Inductance: 2MHz, Rdc = 80 mohm Embedded Inductor Evaluation on Embedded Inductor - Substrate : 2L - Package Height: 0.9mm Embedded Inductor (Simulation) - Size: 2.1 x 1.5 x 0.55 mm - Inductance: 2MHz, Rdc = 70 mohm Advantages of Embedded Inductor: 1- Package height reduction 2- Lower power consumption due to lower Rdc ( P = I 2 * Rdc) 3- Lower EMI concern on PCBA/Package - as most magnetic field are trapped in toroid ferrite Application : PMIC, DC/DC converter
13 Benchmark on Antenna in Package Solutions Package with Elevated Inverted-F Antenna (in package) Antenna Package with Printed antenna (in substrate) Antenna Package with Coated antenna (on package surface) Antenna Antenna Performance - Efficiency, Gain, VSWR Bandwidth,, etc Radiation Pattern Assembly Process Cost Dimension (include Keep out area) Remark Features 1. Antenna in molding Compound 2. Method of frequency adjustment Features 1. Multi-layer antenna to shrink size 2. Special anti-human body design Features: 1. sputter coating on package to form antenna 2. Thin coating layer limit performance 3. Complicate process for signal feeding
14 db(st(port01_t1,port01_t1)) Name X Y m m1 XY Plot 1 HFSSDesign1 Curve Info db(st(port01_t1,port01_t1)) Setup1 : Sw eep Freq [GHz] ANSOFT Antenna and Package Co-Design Information Input & Study 1- Applications 2- Package Size 3- Certification Comply 4- Assembly Structure 5- Required SPEC - Gain - Efficiency - Bandwidth - Radiation Pattern Antenna-Package Co-design 1- Antenna Design/Simulation 2- Substrate Design 3- Total SiP Design Radiation Pattern Sample Build & Verification Performance Verification/Measurement - Gain - Efficiency - Bandwidth - Radiation Pattern Current Density Distribution 1. Package with Elevated Inverted-F Antenna 2. Features : (1) Size Reduction, 2.4GHz antenna in 6.5x6.5mm (2) High Antenna Efficiency > 30%, Gain > 1dBi (3) Support High Density Component in Package (4) Easy for Customer Layout Design 1. Package with Folded Antenna 2. Features: (1) Feasible EMI Shield & Antenna coexistence for Certification (FCC/CE) (2) High Antenna Efficiency > 35%, (3) Anti-Human Body Effect
15 10mm NFC Antenna Development Simulation model Current Antenna SPIL Idea 120um Molding Compound Gold wire 15mm 6 mm x 2mm 500um PP Sub 20um Abracon:ANFCA-1510-A02 Item Current Antenna SPIL Proposal Size(mm) 15 x 10 6 x 2 Operation Freq.(MHz) Inductance(uH) 1.8±10% 2.14 Q Factor min DCR Max.(Ω) Application: Wearable Health care ID scan Ticketing system Status : Target Finish Design by 2015/09, Qaul Pass by 2016/01
16 Example of SiP for IoT / Wearables 75% size reduction 80% size reduction MCU + WiFi COB Solution Size : 22x19mm MCU + WiFi SiP solution Size : 10x10mm MCU + BLE COB Solution Size : 18x12mm MCU + BLE SiP solution Size : 6.5x6.5mm Include WiFi + MCU + Memory Component Count : 50 Process : wafer thinning, stack Die on FC, MUF, EMI Coating Include BLE, EEPROM, X tal, Antenna Component Count : 28 Process : stack die on passives, Antenna in Package, Molding WiFi Plug WiFi Air Conditioner WiFi Bulb BLE Door Lock BLE Toy irhytm WiFi Speaker WiFi Sensor Hub Hearing Aid Swimming Band Hand Band
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