European bespoke wafer processing & development solutions for : Grinding, CMP, Edge Treatment, Wafer Bonding, Dicing and Cleaning

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Ashley Knight
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1 European bespoke wafer processing & development solutions for : Grinding, CMP, Edge Treatment, Wafer Bonding, Dicing and Cleaning Georges Peyre : Sales & Marketing Director SEMICON Europa Grenoble

2 Rockwood Wafer Services Milestones Created in : Major Investment : $7m Capacity & Capability 0,12µ and 0,09µ defects for 200mm Wafer Reclaim : Strategic Diversification Program (Wafer thinning services and sapphire) 2009 : Investment in an ERP system : Investment in a new thinning line. IS0 9001, ISO 14001, OHSAS 18001: Integrated Management System R&D projects (SCS : OPTIM, COMET & Catrene : Master3D)

2008 : Strategic Diversification Program (Wafer thinning services and sapphire) 2009 : Investment in an

3 Rockwood Wafer Services Activities Historical Business Volume : Wafer reclaim: recovery of Test & Product wafers, to be re-used as test wafers. Wafer supply: reclaim or virgin Strip & Clean: layer removal only to supplement or replace internal reclaim. Process mapping: an audit exercise which aim to find rules to reduce cost and optimise wafer usage. Diversified in Wafer Services : Wafer Processing: offering the following types of services Grinding/Thinning (including TAIKO) Dicing (including DBG) Wafer Resizing Edge Shaping / Trimming CMP/Cleaning (wafer surface preparation before Bonding) Wafer Bonding Sapphire substrate reclaim: recovery of substrates to an EPI ready state. Sapphire surface preparation: proprietary cleaning process to de-metalize sapphire substrates for high specification applications.

Process mapping: an audit exercise which aim to find rules to reduce cost and optimise wafer usage.

4 X-Ray detector X X-Ray source X-ray detector Sample to be characterized Back side illumination CMOS wafer Photodiode wafer 4

5 Rockwood Process Flow INSPECTION Thickness meas. Final clean room ADC Si substrate (> 7xx µm) TAPING CMP / Cleanroom 100 ADC Si substrate (> 7xx µm) To protect CMOS side & make the handling safer THINNING ( 2xx µm) CMP / Cleanroom steps: rough + fine wheel ADC Si substrate (~ 2xx µm) The wafer is highly warped and the surface damaged POLISHING ( 2xx µm) + clean 2 steps: bulk + final polish ADC Si substrate (~ 2xx µm) DE TAPING CMP / Cleanroom 100 ADC Si substrate (~ 2xx µm) FINAL CLEAN & Thickness meas Final clean room ADC Si substrate (~ 2xx µm) 5

safer THINNING ( 2xx µm) CMP / Cleanroom 10000 2 steps: rough + fine wheel ADC Si substrate (~ 2xx µm) The wafer is highly warped and the

6 Bonding Process Step. After Surfaces activation Contact is made a bonding wave propagate, generated by a light mechanical pressure Bonding wave front

7 Edge Trimming Removing or, shaping the edge of a wafer is becoming mandatory for some specific applications. For example, a wafer is thinned as part of the process flow and still facing further processing steps. A typical application is when using a carrier wafer to enable backside processing of thin wafers. The edge of the thin wafer gets sharp and very fragile, making any further process steps very difficult to manage. 7

For example, a wafer is thinned as part of the process flow and still facing further processing steps.

9 CERN ALICE LHC Rockwood working with the CERN helping in the development of the ALICE detector experiments on the LHC.

10 Typical wafer processing line Services Bonded Pair Thinning:- Achieve Targeted thickness of one bonded pair substrate, to include Silicon, III/V and or Glass bonded substrates on silicon. Bonding Surface preparation:- Achieve targeted thickness and Surface Microroughness with targeted LPD's Specification. CMP:- Achieve targeted removal or microroughness on Strained SiGe EPI or Silicon. Thin + Double side Polishing:- To thin wafers and achieve low Ra, LPD s and Metallics on both side of the wafer, prepared for subsequent fabrication. SOI thinning:- To thin Handle or Product wafer to specified thickness, Ra, LPD spec and surface metal levels. Pre Packagaging Grinding:- Achieve targeted thickness and surface Ra post wafer fabrication ready for encapsulation and packaging. Wafer carriers:- Ultra Flat Wafers and very low Average wafer to wafer thickness variation wafers Wafer re-sizing:- Able to cut and edge chamfer larger wafers to any standard diameter. Wafer Bonding :- Up to 200mm Silicon, Quartz and other substrates. 10

Thin + Double side Polishing:- To thin wafers and achieve low Ra, LPD s and Metallics on both side of the wafer, prepared for subsequent fabrication.

11 Rockwood: Quality Systems SINCE 2009 : Consolidated in one integrated system: Quality System : ISO 9001:2008 Environment : ISO Safety & Health : OHSAS

12 MASTER_3D MAnufacturing Solutions Targeting competitive European production in 3D

13 SCS Cluster Co-Exhibitor booth number

Figure 1 Wafer with Notch

Figure 1 Wafer with Notch Glass Wafer 2 SCHOTT is an international technology group with more than 125 years of experience in the areas of specialty glasses, materials and advanced technologies. With our high-quality products and