Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs

Transcription

1 The MOSFET

2 Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Assets: High integration density and relatively simple manufacturing process Consequently, it is possible to realize transistors on an integrated circuit (IC) economically.

3 The MOS Transistor Gate Oxide Source n+ Gate Polysilicon Drain n+ Field-Oxide (SiO ) p-substrate p+ stopper Heavily doped n-type source and drain regions are implanted (diffused) into a lightly doped p-type substrate (body) A thin layer (approx. 50 A 0 ) of silicon dioxide (SiO ) is grown over the region between source and drain and is called thin or gate oxide

4 Gate oxide is covered by a conductive material, often polycrystalline silicon (polysilicon) and forms the gate of the transistor MOS transistors are insulated from each other by thick oxide (SiO ) and reverse biased p-n+ diode Adding p+ field implant (channel stop implant) makes sure a parasitic MOS transistor is not formed MOS Transistor as a switch V in > V T : a conducting channel is formed between source and drain and current flows V in <V T : the channel does not form and switch is said to be Open V in >V T : current is a function of gate voltage

5 NMOS, PMOS, and CMOS Technology In an NMOS transistor, current is carried by electrons (from source, through an n-type channel to the drain Different than diode where both holes and electrons contribute to the total current Therefore, MOS transistor is also known as unipolar device Another MOS device can be formed by having p+ source and drain and n-substrate (PMOS) Current is carried by holes through a p-type channel A technology that uses NMOS (PMOS) transistors only is called NMOS (PMOS) technology In NMOS or PMOS technologies, substrate is common and is connected to +ve voltage, GND (NMOS) or VDD (PMOS)

6 In a complementary MOS (CMOS) technology, both PMOS and NMOS transistors are used NMOS and PMOS devices are fabricated in isolated region from each other (i.e., no common substrate for all devices) MOS transistor is a 4 terminal device, if 4th terminal is not shown it is assumed to be connected to appropriate voltage

7 What is an MOS Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D When the voltage applied to the gate is larger than V T, a conducting channel is formed between the drain and source. In the presence of a voltage difference between D & S, electrical current flows between them. When the gate voltage is lower than the threshold, no channel exists, and the switch is considered open. Very few parasitic effects, high integration density, relatively simple manufacturing process

8 Threshold Voltage: Concept S + V GS - G D n+ n+ n-channel p-substrate Depletion Region B Initially: V GS =0, both pn-junctions have a 0V bias, and are considered off => extremely high resistance between drain and source. Then: V GS >0, channel is formed If now the gate voltage (V GS ) is increased, gate and substrate form plates of a capacitor with oxide as dielectric +ve gate voltage causes +ve charge on gate and -ve charge on the substrate side. In substrate it occurs in two steps (i) depletion of mobile holes, (ii) accumulation of -ve charge (inversion)

9 At certain V gs, potential at the interface reaches a critical value, where surface inverts to n-type (start of strong inversion) Further V gs increase does not increase the depletion width but increases electrons in the inversion layer Threshold Voltage where V T = VT + γ[ ΦF + V Φ 0 SB F ] where γ = qεsin C OX A V T is +ve for NMOS and -ve for PMOS devices

10 The Threshold Voltage Body Effect 0.9 V T (V) V T is the V GS value where strong inversion occurs. Note that V BS should never exceed 0.6V, otherwise the source-body becomes forward biased, which deteriorates the transistor s operation V BS (V ) V T T 0 + γ ( ) Φ + V Φ = V F SB F Function in manufacturing process (oxide thickness, fermi voltage, ion implants)

11 Transistor in Linear S V GS G V DS D I D n + V(x) + n + L x p-substrate With V GS >V T, and a small V DS is applied, a current I D flows from the drain to source. Using simple analysis, a first order expression of I D is obtained. When V GS >V T Let at any point along the channel, the voltage is V(x) and gate to channel voltage at that point is V GS -V(x) B

12 If the V gs -V(x) >V T for all x, the induced channel charge per unit area at x (Cox is the capacitance per unit area of the gate oxide ε ox /t ox ) Current is given by The electron velocity is given by Therefore, Qi( x) = COX[ Vgs V ( x) VT] I D = υ ( x ) Q i( x ) W υ n = µ ne ( x ) = µ n dv dx ID dx = µ ncoxw ( Vgs V VT) dv Integrating the equation over the length L yields I D I D = K' = n W L Kn[( V [( V gs gs V V T T ) V ) V ds ds Vds Vds ] ] or For small V DS values, the MOS acts as a resistor

13 Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+ Pinch-off With V GS >V T, and a larger V DS applied, the channel thickness gradually is reduced from source to drain until pinch-off occurs (channel depth depends on the voltage from G to channel). This occurs when pinch-off condition meets the drain region, V GS V DS V T and current remains constant I D kn = W L ( V V ) GS T

14 K n is known as the process trans-conductance parameter and equals K' n C = µ n OX = µ n ε tox If the VGS is further increased, then at some x, V gs -V(x) <V T and that point the channel disappears and transistor is said to be pinched-off Close to drain no channel exists, the pinched-off condition in the vicinity of drain is V GS -V DS V T Under these conditions, transistor is in the saturation region If a complete channel exists between source and drain, then transistors is said to be in triode or linear region Replacing V ds by V gs -V T in the current equation we get, MOS current-voltage relationship in saturation region I D = K' n W L ( V gs ox V T )

15 This equation is not entirely correct, the position of pinch-off point and hence the effective channel length is a function of V ds, a more accurate equation is given as I D = K ' n W gs T L ( V V [1 + λv where is an empirical constant parameter called channel length modulation factor ) ds ] V DS = V GS -V T V GS = 5V I D (ma) 1 Triode Saturation V GS = 4V V GS = 3V Square Dependence 0.00 I D Subthreshold Current V GS = V V GS = 1V V DS (V) (a) I D as a function of V DS 0.0 V T V GS (V) (b) I D as a function of V GS (for V DS = 5V).

16 Current-Voltage Relations A good ol transistor -4 x 10 6 VGS=.5 V 5 4 Resistive Saturation VGS=.0 V I D (A) 3 V DS = V GS -V T Quadratic Relationship VGS= 1.5 V 1 VGS= 1.0 V V DS (V)

17 A model for manual analysis

18 The Transistor as a Switch (for hand analysis) V DS (V DD V DD/ ) V GS V T V DD I D S Ron D R on varies with time, nonlinear and depends on operating point of the MOS. I D V GS = V DD R eq = average t= t1... t 1 Req ( Ron( t ) + R ( R ( on 1 on t ( t)) = t )) 1 t t 1 t 1 R on ( t) dt = t 1 t t 1 t 1 V I DS D ( t) dt ( t) R mid R 0 V DD / V DD V DS

19 The Transistor as a Switch Resistance is inversely proportional to W/L ratio of the device. Doubling the transistor width cuts the resistance by half 7 x For V DD >> the resistance becomes virtually independent of V DD. Only a minor improvement is the resistance can be seen when rising V DD (attributed to the channel length modulation) refer to the I-V equations in linear and saturation Once V DD approaches V T, the resistance dramatically increases. R eq (Ohm) V (V) DD

20 Dynamic Behavior G C GS C GD S D C SB C GB C DB B

21 Dynamic Behavior MOS transistor is a unipolar (majority carrier) device, therefore, its dynamic response is determined by time to (dis)charge various capacitances MOS capacitances Gate oxide capacitance (C g ): C OX = per unit area, for a transistor of width, W and length, L, the C g =C ox.w.l From current equation it is apparent that C ox should be high or gate oxide thickness should be small Gate capacitance consists of several components Source and drain diffusions extend below the thin oxide (lateral diffusion) giving rise to overlap capacitance

22 The Gate Capacitance Polysilicon gate Source n + x d x d W Drain n + t ox L d Top view Gate-bulk overlap Gate oxide n + L n + Cross section Source and drain diffusions extend below the thin oxide (lateral diffusion) giving rise to overlap capacitance X d is constant for a technology and this capacitance is linear and has a fixed value C gso = C gdo = C ox X d W= C o W

23 Average Gate Capacitance Gate to channel capacitance consists of C gs, C gd, and C gb components. All these components are nonlinear and their value depends on operation region of the device. Most important regions in digital design: saturation and cut-off

24 Gate Capacitance G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturation No channel exists, CGC appears between gate and body Inversion layer is formed acting as conductor between source and drain. C gb =0 (body electrode is shielded by channel). CGC divided evenly between source and drain Channel is pinched off. C gd ~0 & C gb ~0 Most important regions in digital design: saturation and cut-off

25 Gate Capacitance WLC ox C GC WLC ox C GC WLC ox WLC ox C GC B C GCS = C GCD WLC ox C GCS C GCD 3 V GS 0 V DS /(V GS -V T ) 1 Capacitance as a function of V GS (with V DS = 0) Capacitance as a function of the degree of saturation

26 Diffusion Capacitance