Packaging Technologies for Smart Systems at Wafer and Panel Level

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1 Packaging Technologies for Smart Systems at Wafer and Panel Level Name Abteilung Klaus-Dieter Lang

2 OUTLINE Introduction Technology Solution Panel Level Packaging Packaging Trends Summary Technology Solution Wafer Level Packaging Summary

3 The World of Smart Smart Cities Diskussionsbeitrag M. Juergen Wolf

4 Customer Requirements for Smart Systems connected, autonomous, miniaturized, safe System integration and assembly Improved materials, energy-efficient and advanced technologies for different application environments Robust, modular, standardized, product adapted Very low cost Data analysis and data security Analysis of very large amounts of data (Big Data) High reliability, data security, no manipulation, clear identification Data transmission End-to-end networking from the system to networking and controlling Transmission of high volumes of data or pre-assessment of data Large bandwidth, real-time, long range High-performance wireless technology Localization Navigation capability, location reference of the system data Usability suitable and easy-to-use for human-machine interfaces

security, no manipulation, clear identification Data transmission End-to-end networking from the system to networking and controlling Transmission of high volumes of data or pre-assessment of data

5 Systemintegration - Challenge Ev ery Application Field Requires Own technology path Specific solutions Timeline to market Infrastructure and supply chain

6 Driving Forces for System Packaging B.Bottoms, B.Chen

7 System Packaging Supply Chain Source: Yole 2014

8 OUTLINE Introduction Technology Solution Panel Level Packaging Packaging Trends Summary Technology Solution Wafer Level Packaging Summary

Technologies for System Packaging Fusion of different technologies Leadframe/ Strip Format 8 Wafer-Level FO Wafer-Level 8 and 12 PCB Technology Embedding 18 x 24 die attach, copper wire bonding

9 Technologies for System Packaging Fusion of different technologies Leadframe/ Strip Format 8 Wafer-Level FO Wafer-Level 8 and 12 PCB Technology Embedding 18 x 24 die attach, copper wire bonding materials and processes mold technology & materials / through mold vias thin film materials / sputtering/ 3D integration advanced PCB processes & materials ready for PLP improvement resolution and accuracy for next Gen PLP LCD Technology 28 x 32 equipment for very large area polymer application metal sputtering

through mold vias thin film materials / sputtering/ 3D integration advanced PCB processes & materials ready for PLP

10 Trend on ICs and Packages 2D -> 3D Intrinsic full 3D 3D by TSV 2.5 D IC Interposer3 D IC Chip w TSV Limited 3D by Wire, Bump and Ball PoP 3D by Via 3D PCB Embedding 3D FO-WLP Stacked Die Hybrid SOP QFP QFN 2D Wire bonded Leadframe Side-by-side Wire bonded Side-by-side Flip Chip Side-by-side FO-WLP Source: ASE + IZM

3D PCB Embedding 3D FO-WLP Stacked Die Hybrid SOP QFP QFN 2D Wire bonded Leadframe

11 Interconnect Resolution Trend PCB BU-IC Pack. Si-BEOL Silicon 1 L/S=4/4um 0,1 0,01 25um UV laser 0, Organic interconnect density is rapidly approaching Si-BEOL

UV laser 0,01 2012 2013 2014 2015 2016 2017

12 Packaging Technologies at Wafer and Panel Level Large-area molding 18" x 24" Fully electrical connected PL embedded package stack with TMV & 3D routing

13 OUTLINE Introduction Technology Solution Panel Level Packaging Packaging Trends Summary Technology Solution Wafer Level Packaging

14 Functionallity / Complexity Wafer Level Integration Flip Chip / MCM-D WLP Flex & Stacked Flex 2.5D WL-SiP TSV Silicon Interposer 3D WL-SiP TSV active IC Interposer TSV Stack egrain TM Integrated Passives Image Sensor Packaging Fine Pitch Bumping Multi Layer Redistribution Chip on Chip (FtF) Thin Chip Integration (BtF) Time

5D WL-SiP TSV Silicon Interposer 3D WL-SiP TSV active IC Interposer TSV Stack

15 Specification Si-Interposer - Roadmap TSV IP 20 µm TSV (ASR>5) RDL (2 + FS, L/S 10) TSV IP 10 µm TSV (ASR: >10) RDL (2+FS, 2+BS, L/S <5 µm) TSV IP 10 µm TSV (ASR: >12) RDL (2+FS, 2+BS, L/S<5 µm, ox diel. Glas IP TGV > 20µm; RDL (2+FS, 2+BS, L/S 10) TS V-IP w. integrated passives TS V-IP w. embedded active & integrated passives TS V-IP w. electrical/optical interconnects TS V-IP electr/opt; active cooling Modular Active IP Year

Glas IP TGV > 20µm; RDL (2+FS, 2+BS, L/S 10) TS V-IP w. integrated passives TS V-IP w.

16 3D Market S ource:yole

17 OUTLINE Introduction Technology Solution Panel Level Packaging Packaging Trends Summary Technology Solution Wafer Level Packaging

18 Panel Level Packaging Embedding Process courtesy AT&S

19 Panel Level Molding Panel-Size FO Packaging PCB Embedding Substrates Large-area molding 18" x 24" Through mold vias for 3D Interconnects using PCB materials & technology mold embedding of sensors use of new polymers / laminates thin layers (10 µm) for high density high breakthrough (>40 kv/mm) for power improved resolution for interconnects 10 µm 5 µm 2 µm processes to reduce warpage

sensors use of new polymers / laminates thin layers (10 µm) for high density high breakthrough

20 IC Substrate Technologies Shinko's thin-film RDLs on buildup package substrate 2 µm Line/Space Prototypenstatus! Roadmap: Fine Line and Via Line: 8/8, 5/5, 3/3, 2/2, 1/1 µm Via: 60, 50, 40, 30, 20 µm

(source Yole) Smart Phone Market DC/DC converters Power management units Connectivity module

21 Embedding Application Power and Logic The production of embedded packages is ramping up fast Today 2013: 340 Mio., Forecast 2016; 1700 Mio. (source Yole) Smart Phone Market DC/DC converters Power management units Connectivity module Computer market MOSFET packages Driver MOS SiPs PCB Embedding Technology is implemented or will come soon at PCB manufacturers Semiconductor manufacturers OSATS

22 Embedded Active Market Forecast (millions) Source: TechSearch International, Inc. Integrated power management devices in laminate packages Power devices such as voltage regulators Automotive such as modules with embedded IGBTs RF modules Fan-out WLP PoP with embedded application processor Medical (hearing aids, etc.) Potential high v olum es for battery charging applications

23 OUTLINE Introduction Technology Solution Panel Level Packaging Packaging Trends Summary Technology Solution Wafer Level Packaging

0 Ultra Thin core 0.5 0.0 Tim e Automotive, Medical Industrie 4.

24 Package Thickness (mm) System Packaging of Tomorrow Dual Integration? Miniaturization Cost Performance Source: Intel 1.5 Coreless Die Embedding 1.0 Ultra Thin core Tim e Automotive, Medical Industrie 4.0, Robotic Internet of Things Consumer RF-Modules Mobile Wireless Camera with image processing Trillion Sensor Vision X-ray of embedded µsd

25 Application Example: Smart Sensor System TSV Interposer (10/100) with MEMS and ASIC assembled on organic board Project: Optopack (Funding State of Saxony, Partner MPD)

26 Key Challenges EDA Tools T(X)V Integration Wafer and Substrate Handling / Temp Bonding De-Bonding /Thinning Fine Pitch Assembly / 3D Stacking Advanced Test (KGD, ) Performance Optimization (electrical, thermal, optical ) Cost / Yield

Fraunhofer IZM Thank you for your attention! Contact: Prof. Dr.-Ing. Dr. sc. techn. Klaus-Dieter Lang Email: kdlang@izm.fraunhofer.

28 Fraunhofer IZM Thank you for your attention! Contact: Prof. Dr.-Ing. Dr. sc. techn. Klaus-Dieter Lang Fraunhofer Institute for Reliability and Microintegration IZM Gustav-Meyer-Allee Berlin, Germany web:

Dual Integration - Verschmelzung von Wafer und Panel Level Technologien

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