Autarkic Distributed Microsystems new Dimensions of Miniaturization

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1 Autarkic Distributed Microsystems new Dimensions of Miniaturization Klaus-Dieter Lang, M. Jürgen Wolf, Fraunhofer IZM; TU Berlin () Seite 1

2 Outline Introduction Requirements to System Integration Technologies Advanced Technology Solutions for Miniaturized Systems System integration at wafer and chip level System integration at substrate level Conclusions Seite 2

Miniaturized Systems System integration at wafer and

3 Definition of Smart Systems Integration of Different Functionalities such as sensors, actuators, photonics, signal processing, data transmission, power supply with a high degree of miniaturization and flexibility at reasonable costs in a Package, that bridges the Gap between Nano-Electronics and Application is adopted to the application environments Seite 3

degree of miniaturization and flexibility at reasonable costs in a Package, that bridges

4 Future Application Fields of Microsystems agriculture food textiles Home appliances illumination Sporting goods Seite 4

5 Requirements to System Integration Technologies Seite 5

6 eterogeneous System ntegration heat sink Heat physical chemical biological parameters Sensors Actuators energy management ICs passives wireless RF antenna Wireless Data Transmission Provide Information in network environment Sensor Interface Energy Signals IO-Power Interface Ultra Small Smart Sensor System Seite 6

antenna Wireless Data Transmission Provide Information in network environment

7 xample- Grain Basic Construction Analog Circuits AD-Converter DA-Converter Memory Passive Components Antenna RF-Frontend Micro Processor Sensors Actuators Energy Storage / Conversion egrain Functional Layer Seite 7

Antenna RF-Frontend Micro Processor Sensors Actuators

8 3D-System Design Methodology Self-Sufficient Distributed Micro Systems System Design Functionality Application / Environment System Layout Miniaturization Energy Supply Packaging Environmental Interface Data Handling Communication Interface Sensors Actuators Signalers Crystals Antennas Hardware Technology Interfaces Software Energy Supply Packaging Analog Circuits Digital Circuits RF Circuits Sensors Actuators Signalers Crystals Antennas M. Niedermayer, IZM Berlin Seite 8

Interface Sensors Actuators Signalers Crystals Antennas Hardware Technology Interfaces Software Energy Supply

9 System Architecture µc: 8bit RF: 0,3-1GHz µc: 16bit RF: 2,45GHz µc: 16bit RF: 24,5GHz Antenna Functionality Energy Efficiency Volume Distance Bandwidth Maximum Volume High High Long Slow Low Small Low Small Short Fast High Large High Small Short Fast High Large Life time Best at Short Data packets Best at Long Data packets M. Niedermayer, IZM Berlin Seite 9

High Long Slow Low Small Low Small Short Fast High Large High Small Short Fast High Large

10 Advanced Technology Solutions for Miniaturized Systems Wafer and Chip Level Seite 10

11 Chip-to-Wafer Stacking by ICV-SLID Technology Vertical System Integration of SiGe and Si devices HS (650 µm) and SiGe-Top Chip Top SiGe chip, 20 µm thick, stacked on bottom Si device, handling substrate (HS) removed Si-Bottom Wafer (Source: Fraunhofer IZM Munich) Seite 11

Top SiGe chip, 20 µm thick, stacked on bottom Si device, handling

12 Chip-to-Wafer Stacking by ICV / CuSn - Soldering Fabrication of Tungsten-filled InterChip Vias on Top Substrate Via Opening and Metallization Thinning Opening of Plugs Si 10 µm Electroplating Alignment and Soldering (P. Ramm, C. Landesberger, et al. IZM Munich) Seite 12

Metallization Thinning Opening of Plugs Si 10 µm Electroplating

13 F2F-SLID Technology thinning to 10 µm C2W-Transfer After Chip Transfer from Intermediate Handling Wafer to Target Substrate Chip Thickness 500 µm After Thinning on Target Substrate Chip Thickness 10 µm (R. Wieland, R. Merkel, A. Klumpp, P. Ramm, IZM-M) Seite 13

Chip Thickness 500 µm After Thinning on Target Substrate Chip

14 Thin Chip Integration on Wafer Level Silicon Chip/Wafer thin chips [40 µm] embedded into redistribution BCB/Cu (M. Töpper, O. Ehrmann, K. Buschick, et al. IZM Berlin) Seite 14

15 Thin Glas Layers for Integrated Passives glas as dielectric layer for capacities Kondensator BCB Cu Cu Glas (1 µm) glas passivation for thinfilm resistors BCB Cu Glas (1 µm) NiCr Widerstand (K. Zoschke, J. Wolf, C. Lopper, M. Lutz, M. Toepper, O. Ehrmann, IZM-Berlin) In cooperation with Seite 15

thinfilm resistors BCB Cu Glas (1 µm) NiCr Widerstand (K. Zoschke, J.

16 Basic technologies: Bonding and deep RIE Fixed electrode SiO 2 Wire bonding pads (Al) Resonator structure Si Pre-etched cavity Si Encapsulated structures (direct bonding, glass fritt bonding) Trenches for insulation Anchor Tunable IR detector (InfraTec GmbH Dresden) Vibration sensor (Siemens) Step-by-step switchgear Angular rate sensor (LITEF GmbH Freiburg) (K. Hiller, M. Wiemer, Th. Gessner, IZM-C) Seite 16

Trenches for insulation Anchor Tunable IR detector (InfraTec GmbH Dresden) Vibration sensor (Siemens)

erformance of encapsulated afer level batteries battery assembly at wafer charge discharge cycle stability demonstrated > 200 cycles (67% capacity remaining) encapsulated as laminated type 1 type 2

17 erformance of encapsulated afer level batteries battery assembly at wafer charge discharge cycle stability demonstrated > 200 cycles (67% capacity remaining) encapsulated as laminated type 1 type 2 area [cm²] charge current = discharge current = 1.5 ma thickness [µm] capacity [mah] K. Marquardt, R. Hahn, T. Luger (IZM Berlin) energy density [mwh/cm³] Seite 17

2 area [cm²] 0.96 0.96 charge current = discharge current = 1.

18 ntegrated Passive Devices Single components as well as more complex passive structures like resistor networks or filters can be summarized in single devices Integrated Passive Devices (IPD) IPDs containing all three passive types (R, L, C) can be realized in various forms and sizes with flip chip interconnects as well as wire bond pads D with 3 inductors and 2 pacitors The IPDs are completely processed at wafer level on different substrates like silicon, glass or alumina After dicing the IPDs are ready for mounting IPD with 63 resistors (M. Töpper, O. Ehrmann, K. Buschick, et al. IZM Berlin) Seite 18

interconnects as well as wire bond pads D with 3 inductors and 2 pacitors The IPDs are completely processed at wafer level on different substrates like

19 Wafer-Level-Packaging for Optical Applications Via-holes and dicing steets etched in one step Ball Grid Array with Silicon Via Contacts (M. Töpper, O. Ehrmann, et al. IZM Berlin) Seite 19

20 Advanced Technology Solutions for Miniaturized Systems Substrate Level Seite 20

21 Wireless Sensor Module Sensor Unit Sensor Unit: Sensors (Temp. LM20, Photoresistor NSL19), LEDs & Switches Analog Sensor Data µc Unit µc Unit: Controller (ATMega128L, 8Bit), Quarz and Passives RF Unit: Transceive 868MHz (ChipCon1000), Digital Sensor/Protocol Data Signal RF Unit Power Unit Basics Size 26 x 26 x 24 mm Power consumption max. 20mA / 3V Power: Battery (CR2354 3V/560mAh) Stand-by Current 10µA (1 year at nominal battery capacity) Light and temperature sensor FhG IZM ASE System Integration M. Niedermayer Seite 21

22 Example for a Temperature sensor Node Unitized System Development Circuit Design 3D-Visualisierung Prototype Seite 22

23 Example for a Temperature sensor Node COB Technology for Microcontroler Assembly Die-Bonding Wire Bonding (Al-Wire, Ø 25 µm) Glob-Top with Frame Seite 23

24 Example for a Temperature sensor Node SMD-Assembly of individual system levels Stencil printing Pick and Place Reflow Seite 24

25 Example for a Temperature sensor Node 3D - PCB Stacking Adjustment Compressing of the Package Soldering with Vapour Phase Separating Seite 25

26 Design and simulation of the package Seite 26

27 cceleration Sensor System CB Stacking Technology capacitor op-amplifier RF transceiver controller sensor sub-module 2 frame sub-module 1 frame (K.-D. Lang, S. Schmitz, V. Großer, P. Semionyk, IZM Berlin) Seite 27

28 egrain integration into a sensor network Seite 28

29 Chip in Polymer build-up layer filled through hole embedded chip and via to chip pad Cross section of a single stack package via to board metallization solder ball 0.5mm FR4 board Stack of 4 single packages (A. Ostmann, R. Aschenbrenner, et al. IZM Berlin) Seite 29

chip module design Cu conductors to embedded chip (L.

30 Multiple Levels of Chip Embedding embedding of 4 layers of chips on a 500 µm FR4 core Via to embedded chip module design Cu conductors to embedded chip (L. Böttcher, D. Manessis, A. Ostmann, IZM Berlin) Seite 30

31 World smallest Wireless Sensor Node with ad-hoc network capability Mica 2 architecture frequency: 868 MHz data rate: 40 kbit/sec transmission range: 2m Sensors: temperature, light Technology: flexible substrate flip chip interconnects passive device integration Seite 31

32 Miniaturized Packaging Solution for a integrated Microphone InFON Si-Mic Packages Public project InFON Development of a miniaturized packaging solution for a stress sensitive Si microphone Project Result: A generic packaging technology for stress sensitive devices. Substrate is low cost FR4 Mold cap is made from Duromer allowing metallization / sound port realization Assembly technology is compatible to COB Further Miniaturization Potential: Volume reduction by the use of Duromer MID technology for 3D packaging uromer MID Package Schematic (K.-F. Becker, P. Meier, M. Koch, P. Sommer, IZM Berlin) (funded by BMBF Germany) Seite 32

33 erebral Cortex Neural ecording Array Advantage of implanted electrodes compared to electrodes on scalp: signals are stronger, steeper and not jumbled electrodes listen to individual cells allowing faster response and less training Inductors (Au/Pi Flex Technology 3 Layers Pi 2 Layers Au 1 Layer Ni/Au (Cooperation with the University of Utah) Seite 33

34 Conclusions Seite 34

35 e Grain - Roadmap PCB-FR4 TQFP, TSOP size: cm volume: cm³ HDI-FR4 CSP, COB, FC size: 0, cm volume: 0, cm³ Flex MCM-L size: 0,7... 1,5 cm volume 0, cm³ 2005 Flex MCM-D size: 0, cm volume 0, cm³ Chip Level 3D size: Wafer Level VSI 0,5... 0,6 cm volume size: 0,1... 0,2cm³ 0, ,5 cm volume 0, ,1 cm³ Seite 35

36 Thank you for your attention! Seite 36

Dual Integration - Verschmelzung von Wafer und Panel Level Technologien

ERÖFFNUNG DES INNOVATIONSZENTRUMS ADAPTSYS Dual Integration - Verschmelzung von Wafer und Panel Level Technologien Dr. Michael Töpper BDT Introduction Introduction Why do we need such large machines to