Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications

Transcription

1 Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications M.Sumathi, 2 S.Malarvizhi Department of ECE,Sathyabama University,Chennai-9 Department/ECE, SRM University, Kattankulathur malarvizhi@rediffmail.com, 2 sumaopi6@mail.com Abstract In this paper, low voltae desin concepts and new CMOS front-end circuits for 2.4GHz wireless applications are presented. The performances of these circuits are analysed and compared with other existin structures usin TSMC 0.8-µm CMOS technoloy scale. The desin trade-offs between impedance matchin, power ain and noise fiure of low-noise amplifiers are hihlihted. The advantae of the introduced mixer topoloy is expressed in terms of conversion ain, noise fiure and linearity. At a supply voltae of.8v, the desin and performance analysis have been performed usin Ailent s Advanced Desin System (ADS09) software. Keywords-CMOS,Front-end, NA, Mixer, Radio Frequency. I. INTRODUCTION Today an increasin market demand for RF transceivers operatin in the 2.4GHz consumer based wireless applications such as mobile phones and wireless local area networks. CMOS is one of the best interation technoloies suitable for desinin RF circuits and systems under deep submicron technoloy scale. The development of hih performance Radio Frequency (RF) transceivers or multistandard/reconfiurable receivers requires innovative RF circuit desin to make the best of a ood technoloy. Another aspect for realization of analo circuits in CMOS technoloy is the possibility of reduction of supply voltae with each technoloy eneration. The selection of receiver architecture is based on hih performance and less number of off-chip components. The followin are the existin receiver topoloies such as Zero-IF, Heterodyne, ow-if and wide-band IF in RF transceivers. Recent research works proved that zero-if always the popular and widely used for RF applications, amon these four architectures. At the same time, heterodyne architecture can provide sufficiently low noise fiure but more external filter circuitry required which also increases receiver size and power dissipation. So that, Direct Conversion (DCR) or zero-if or Homodyne receiver is always the best because it uses less number of off-chip components and less power consumption. The down-conversion architecture produces an imae at zero frequency, thus no imae filter is required. Many short rane 2.4GHz receivers have been desined with a hiher supply voltae and with different technoloy scale []. Several low- power sinle-ended NA desins have been reported with different frequency bands, such as 900MHz, 2GHz. These NA desin needs additional balun circuitry to convert sinle-ended output into differential output [2]-[6]. Also, the second staes of receiver s are the mixers which require only sinal to be fed from a differential source. Amon the various CMOS mixer research, passive and active mixers can have low conversion ain and hih noise fiure (NF)[8]-[2]. Such a hih NF will limit the sinal to noise ratio of the front-end. At the same time, existin circuit topoloies cannot satisfy the required wireless specifications under low voltae operation. Hence it is of interest to introduce new wireless Direct Conversion receiver front-end components that can handle successfully low supply voltaes. The choice of receiver architecture, circuit topoloy desin and systematic optimization of the front-end blocks is always necessary. Basically, front-ends are responsible for trackin weak sinals (RF) at hih frequency and translatin into IF sinals for transmittin with hih power levels. It is an interface between the antenna and diital modem of the wireless receiver. Therefore, it needs hih performance analo circuits like RF amplifier (NA), Mixer and Oscillator. The simplified block diaram of a Direct Conversion Receiver front-end is shown in Fi. It represents the process of 2.4GHz incomin RF sinal frequency (f RF ) by the NA and down-converted into 50MHz intermediate frequency (f IF ) by the mixer. Fi.. Block diaram of RF receiver front-end 8

2 II. NA DESIGN A low noise amplifier (NA) bein the first stae of the receiver front end and it is used to increase the power sinal comin from the antenna while introducin little noise by the same NA. Its main function is to provide enouh ain to overcome the noise of next staes. The receiver s sensitivity is mainly depends upon the NA noise fiure and ain. Bein the first ain stae of the receiver, it should also satisfy the followin objectives such as accurate input/output matchin, minimizin the noise fiure and providin a hih ain with ood linearity. In eneral, the NA structure composed of impedance matchin block for input, output section and amplification block. In this work, NA amplification block is modified for better noise fiure and ain. The amplification block is constructed by dual transistors in CS stae, shown in fi.2. Also an inter-stae inductor is added in between the staes for improvin the impedance matchin. Fi.2.Sinle CS stae usin two transistors Usin this principle, two new NA structures are realized in sinle-ended and differential topoloies. Fi.3 represents the schematic of proposed NA architecture. It comprises an input stae inductor, inter-stae inductor IS,dual CS transistors M,M2, sinle CG transistor M3 and output impedance matchin inductor d. Fi.4.Equivalent model of input stae The simplified theoretical expressions for input impedance and output impedance of the dual CS stae is developed from equivalent circuit, shown in fi.4.the ate-source capacitances and drain-source currents are paralleled in this model. C s, C s2 and G,2 V s represents the ate-to-source capacitances and drain-source currents. The input impedance seen at the ate of M is calculated by usin eqn.. R s in = () Cs + Cs2 With the help of operatin frequency ω o and the ate-tosource capacitance, the optimized width of the transistors can be calculated. The output impedance of the common source stae with inter-stae matchin inductor is calculated by usin eqn. (2) Z + C + ) ( C s out = Sis + (2) S( Cds ds2 ds + Cds2 ) C ds, C ds2 are the drain-to-source capacitances of the transistors M,M2. The optimized transistor widths and inductor values are calculated by usin the followin desin equations for performance analysis. The desin steps are elaborated throuh these desin factors. Gate inductance ( ) Gate source capacitance (C s ) Width of the transistor (W) The centre frequency =2 f 0 (3) Fi.3. Schematic of Sinle-ended Dual-CS (SDC) NA =2 2.4*E 9 = E 9 rad/sec is calculated by usin eqn.(3) The value of (ate inductance) is realized by means of eqn.(4). The Q of an inductor value is selected as 8, based on 9

3 0.8-µm CMOS scale characteristics. The source impedance is assumed to be 50ohms. Q R s = (4) ωo = = *E -9 H The ate source capacitance (C s ) is expressed in terms of RF frequency, shown in eqn.(5). s is equal to nh. C s = (5) π f ( + ) o s The calculated values are substituted in their respective places in the schematic and are simulated to evaluate the performance of the desined circuit. With the transistor width at 97µm, the NA achieved the optimum performance in terms of ain, noise fiure and impedance matchin for this desin. Dual-CS Differential NA is constructed by usin two sinle-ended NA s and its structure shown in Fi.5. The desin calculations are the same as that of Dual-CS sinle ended NA. In addition, the values of drain inductors are calculated by assumin C out as pf in eqn.(9). C = (9) D 2 2 4π f o out = = =0. pf From the technoloy scale characteristics, the values of min =0.8E -6 m, T =4.E -9 m are observed. Permittivity of ide is calculated by usin this eqn.6, ε = ε ε (6) o s where is the dielectric constant for free space, which is equal to 8.854E -4 F/cm and dielectric constant of silicon is equal to 3.9. Therefore, ide capacitance is calculated by usin eqn.(7) C ε = (7) T Fi.5. Schematic of Differential Dual-CS (DDC)NA The other existin NA structures such as Cascode sinle-ended NA, differential NA are also desined usin 0.8-µm technoloy scale. The schematics are shown in fi.6&fi E -8 F/um 2 The optimized width of the transistors are calculated by usin eqn.(8). The sizes of the transistors are assumed to be equal in dual CS stae. W 2C 3C s = (8) min Therefore, width W = Fi.6. Sinle-ended Cascode NA W = m

4 Fi.8 represents the Folded Gilbert mixer whose RF &O staes have been biased separately. The other two structures are Inductive coupled and Transconductance mixers,which are shown in Fi.9&0. The first topoloy consists of four nmos transistors (M5-M8) in transconductance stae, and the second desin composed of only two transistors M5,M6 with interstae matchin inductor.. Fi.7. Differential NA III. MIXER DESIGN A down-conversion mixer is always followed by the RF ownoise amplifier. It is one of the most important parts and used to translate one frequency into another. It chanes the RF sinal into IF output sinal. IF sinal frequency is the difference between RF and ocal oscillator sinal frequencies. Mixer plays an important role in improvin the overall system linearity. The proposed mixer desins based on doublebalanced, active mixer topoloy and mainly developed for low voltae applications. There are two modifications done here, one in transconductance stae, another in biasin. The RF staes are completely revised in both desins. In order to utilize the low supply voltae both RF and O staes have been biased separately and it is done with passive elements such as resistors. The first desin uses series form of transistors and the second one uses inductors at RF input stae for providin better impedance matchin and reducin noise fiure. Fi.9. RF stae of Transconductance mixer Fi.0. RF stae of Inductive Coupled mixer The use of folded technique is only to increase the bias current throuh the transconductance stae without increasin the current throuh the switchin transistors. It needs smaller O drive voltae to drive the switchin transistors and thereby improves the switchin efficiency. In order to reduce flicker noise, transconductance stae is altered by addin inductors and s at the ate and source terminals of the RF transistors. Additionally, an inductor with nh is added in between the staes to achieve ood performances of mixer in terms of conversion ain and noise fiure. The size of the transistors are calculated by evaluatin m and C desin formulas. and s inductors used not only for reducin the noise fiure but also, the input impedance matchin at 50 ohm. Their values are 0nH and 0.5nH respectively. The width of the transistor is evaluated by usin this eqn. 9. Fi.8. Folded Gilbert mixer 2

5 W = 2K 2 m n I DS (9) freq= 2.400GHz db(s(,))= where is the channel lenth of the transistor and is the drain to source current. Here m = 0.02, = 0.8 um and I DS is assumed to be 3mA K n ε insε oμ D = is the process dependent term where D is the ide thickness and is the permittivity of insulator. o is the permittivity of free space and is the mobility of chare carriers. The typical values of these factors are substituted and calculated the optimized width of the transistors. W = = um IV. RESUTS Front-end desin evaluations are performed at 2.4GHz RF frequency and 2.25GHz O frequency. The front-end circuits performance is analyzed by usin Intel Core2DuoCPU E7400@2.80GHz processor with Ailent s Advanced Desin System (ADS) 09 version software. The desin simulation process has been carried out in a standard TSMC 0.8-μm CMOS process technoloy. The simulation environment offers reat flexibility in investiatin the performance characteristics of front-end subsystems. The various parameters analysed here are S parameters (S2,S), noise fiure and conversion ain to describe NA and mixer performance with a supply voltae of.8v. Simulation parameters with their values are described in the Table-. TABE. Simulation Input Variables freq= 2.400GHz db(s(2,))= db(s(,)) db(s(2,)) freq, GHz Fi.. S-parameters of Dual-CS Differential NA The noise fiure of NA should remain below 4 db at 2.4GHz in order to prevent inducin noise problems in other staes of the receiver; like mixer, voltae ain amplifier etc. The noise fiure raph of the proposed NA desin satisfied this constraint and it is iven below in fi.2. nf(2) freq, GHz Fi.2. Noise Fiure of Dual-CS Differential NA freq= 2.400GHz nf(2)=2.709 Parameters Source/oad impedance RF frequency O frequency RF power O power Values 50 /500ohms 2.4GHz 2.25GHz -30dBm 5dBm The dual-cs Differential NA raphs of S parameter analysis with respect to RF frequency which lies between the rane of.0 to 3.0 ia hertz are iven below in Fi.. The value of the input impedance matchin can be obtained as db. The value of forward ain S 2 is reached as db, indicated by markers &. Fi.3. Performance Comparison of NA s The performances of other NA s have been observed and compared,shown in Fi.3. The conversion ain of a mixer is defined as the ratio of the desired IF output to the RF input. If the ratio is less than one, it is referred as conversion loss. The conversion ain of a mixer is important because it supports to 22

6 determine the noise fiure and linearity of the overall system. It is plotted as the function of O_power in dbm. Fi.4. shows the conversion ain of the mixer. It has a value of db at O_power of 5 dbm. The noise fiure of the mixer is observed as 7.9dB and the raph is iven in Fi.5. optimum NA, Mixer desin for the proposed confiuration has been iven. Several topoloies of NA, Mixers were first studied, analysed and also utilized for performance comparison study. DDC NA and inductive coupled mixer shows ood performance improvement in all performance factors by % than other circuits. db ConvGain *lo0(nf(3)[0]) O_power O_power= ConvGain=2.276 Fi.4. Conversion of Gain Inductive Coupled Mixer CG 7.6 O_power O_power= *lo0(nf(3)[0])=7.907 Fi.5. Noise Fiure of Inductive Coupled Mixer NF GHz Mixer CG 2.27 Fi.6. Performance Comparison of Mixers 6.04 The performance of Mixers have been analysed and hihlihted in Fi.6. The proposed mixers compared with folded Gilbert mixer. V.CONCUSION In this paper, front-end circuits suitable for 2.4GHz wireless applications were presented. The demonstrated front-end circuits include NA and Down-Conversion Mixers. The theoretical backround is discussed and the formulae of Folded Gilbert Inductive coupled mixer Transconductance mixer NF CG NF REFERENCES [] J.A.M.Jarvinen et al., 2.4GHz receiver for Sensor Applications, IEEE Journal of Solid State Circuits,vol.40,N0.7,pp ,July 05. [2] Arthur Nieuwodt, et al. Desin techniques for reducin the impact of component variations on narrow-band low noise amplifiers, Analo Inter Circ Si Process, Spriner Science Journal, No.55pp.89-93,08. [3] Trun-lien Nuyen,et al., CMOS ow-noise amplifier desin optimization techniques, IEEE Trancactions in Microwave theory and techniques,vol.52,no.5,pp ,04. [4] Ahmed A.Youssef, Desin uidelines for the noise optimization of a 0.8µm CMOS ow noise amplifier, Analo Inter Circ Si Process, Spriner Science Journal,No.46,pp.93-,06. [5] Baimei iu, et al., An Ultra-ow Voltae and Ultra- ow Power 2.4GHz NA Desin, Radio Enineerin, vol.8, No.4, pp ,09. [6] P.Andreani, H.Sjoland, Noise optimization of an inductively deenerated CMOS low noise amplifier, IEEE Transactions on Circuits &Systems, vol.48, No. 9, pp ,0. [7] Tae-Sun Kim, et al.., Post-inearization of Differential CMOS NA Usin Cross-Coupled FET s, Journal of Semiconductor technoloy and Science, vol.8,no.4,december 08. [8] Jenn-Tzer Yan.et al., A 2.4GHz ow power Hihly linear mixer for Direct-conversion receivers, International journalof circuits, systems &sinal processin,vol.no2,07 [9] Vidojkovic.V, et al., A low-voltae folded-switchin mixer in 0.8μm CMOS, IEEE Journal of solid-state circuits, vol.40, no.6, , 05. [0] Park.J,ee.C,Kim.B, Desin and analysis of low flicker-noise CMOS mixers for direct conversion receivers, IEEE transaction on Microwave theory and techniques,vol.54 no.(2), ,06. [] Jenn-Tzer Yan, et al., A 2.4GHz ow Power Mixer for Direct Conversion Receivers, International Journal of Circuits,Systems and Sinal processin,issue 2,vol.,07. [2] Wan-Rone iou,et al., Desin and Implementation of 2.4GHz CMOS Front-end for Wireless Communication, Journal of Marine Science and Technoloy,vol.3,No.3,pp.70-75, 05. [3] Mihai A.T.Sanduleanu, Maja Vidojkovic, Arthur, Receiver Front- End Circuits for Future Generations of Wireless Communications, IEEE Transactions on Circuits and Systems II, vol.55, No.4, April 08. [4] M.Arasu,et al, A 2.4GHz CMOS RF front-end for wireless sensor network applications, IEEE Radio Frequency Interated Circuits Symposium,