BJT Amplifier Circuits


 Henry Bradley
 4 years ago
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1 JT Amplifier ircuits As we have developed different models for D signals (simple largesignal model) and A signals (smallsignal model), analysis of JT circuits follows these steps: D biasing analysis: Assume all capacitors are open circuit. Analyze the transistor circuit using the simple large signal mode as described in pp A analysis: 1) Kill all D sources 2) Assume coupling capacitors are short circuit. The effect of these capacitors is to set a lower cutoff frequency for the circuit. This is analyzed in the last step. 3) Inspect the circuit. If you identify the circuit as a prototype circuit, you can directly use the formulas for that circuit. Otherwise go to step 3. 3) eplace the JT with its small signal model. 4) Solve for voltage and current transfer functions and input and output impedances (nodevoltage method is the best). 5) ompute the cutoff frequency of the amplifier circuit. Several standard JT amplifier configurations are discussed below and are analyzed. For completeness, circuits include standard bias resistors and. For bias configurations that do not utilize these resistors (e.g., current mirror), simply set =. ommon ollector Amplifier (mitter Follower) D analysis: With the capacitors open circuit, this circuit is the same as our good biasing circuit of page 91 with c = 0. The bias point currents and voltages can be found using procedure of pages c V A analysis: To start the analysis, we kill all D sources: V = 0 c c 60L Lecture Notes, Spring
2 We can combine and into (same resistance that we encountered in the biasing analysis) and replace the JT with its small signal model: c v _ i r π β i i r o c i r π r o β i The figure above shows why this is a common collector configuration: collector is shared between input and output A signals. We can now proceed with the analysis. Node voltage method is usually the best approach to solve these circuits. For example, the above circuit will have only one node equation for node at point with a voltage : r π 0 r o β i 0 = 0 ecause of the controlled source, we need to write an auxiliary equation relating the control current ( i ) to node voltages: i = r π Substituting the expression for i in our node equation, multiplying both sides by r π, and collecting terms, we get: [ ( 1 (1 β) = 1 β r π 1 )] [ = 1 β r ] π r o r o Amplifier Gain can now be directly calculated: A v = 1 r π 1 (1 β)(r o ) Unless is very small (tens of Ω), the fraction in the denominator is quite small compared to 1 and A v 1. To find the input impedance, we calculate i i by KL: i i = i 1 i = r π 60L Lecture Notes, Spring
3 Since, we have i i = / or i i i = Note that is the combination of our biasing resistors and. With alternative biasing schemes which do not require and, (and, therefore ), the input resistance of the emitter follower circuit will become large. In this case, we cannot use. Using the full expression for from above, the input resistance of the emitter follower circuit becomes: i i i = [r π ( r o )(1 β)] and it is quite large (hundreds of kω to several MΩ) for. Such a circuit is in fact the first stage of the 741 OpAmp. The output resistance of the common collector amplifier (in fact for all transistor amplifiers) is somewhat complicated because the load can be configured in two ways (see figure): First,, itself, is the load. This is the case when the common collector is used as a current amplifier to raise the power level and to drive the load. The output resistance of the circuit is o as is shown in the circuit model. This is usually the case when values of o and A i (current gain) is quoted in electronic text books. V V c c = L L is the Load Separate Load c r π c r π i β i i β i r o r o L o o Alternatively, the load can be placed in parallel to. This is done when the common collector amplifier is used as a buffer (A v 1, i large). In this case, the output resistance is denoted by o (see figure). For this circuit, JT sees a resistance of L. Obviously, if we want the load not to affect the emitter follower circuit, we should use L to be much 60L Lecture Notes, Spring
4 larger than. In this case, little current flows in L which is fine because we are using this configuration as a buffer and not to amplify the current and power. As such, value of o or A i does not have much use. When is the load, the output resistance can be found by killing the source (short ) and finding the Thevenin resistance of the twoterminal network (using a test voltage source). c i r π r o β i i T v T o KL: i T = i v T r o β i KVL (outside loop): r π i = v T Substituting for i from the 2nd equation in the first and rearranging terms we get: o v T i T = (r o ) r π (1 β)(r o ) r π (r o) r π (1 β)(r o ) = r π (1 β) r π β = r e where we have used the fact that (1 β)(r o ) r π. When is the load, the current gain in this amplifier can be calculated by noting i o = / and i i / as found above: A i i o i i = In summary, the general properties of the common collector amplifier (emitter follower) include a voltage gain of unity (A v 1), a very large input resistance i (and can be made much larger with alternate biasing schemes). This circuit can be used as buffer for matching impedance, at the first stage of an amplifier to provide very large input resistance (such in 741 OpAmp). As a buffer, we need to ensure that L. The common collector amplifier can be also used as the last stage of some amplifier system to amplify the current (and thus, power) and drive a load. In this case, is the load, o is small: o = r e and current gain can be substantial: A i = /. Impact of oupling apacitor: Up to now, we have neglected the impact of the coupling capacitor in the circuit (assumed it was a short circuit). This is not a correct assumption at low frequencies. The coupling capacitor results in a lower cutoff frequency for the transistor amplifiers. In order to find the cutoff frequency, we need to repeat the above analysis and include the coupling capacitor 60L Lecture Notes, Spring
5 impedance in the calculation. In most cases, however, the impact of the coupling capacitor and the lower cutoff frequency can be deduced be examining the amplifier circuit model. onsider our general model for any amplifier circuit. If we assume that coupling capacitor is short circuit (similar to our A analysis of JT amplifier), v i =. V i c V i i o AV i Voltage Amplifier Model When we account for impedance of the capacitor, we have set up a high pass filter in the input part of the circuit (combination of the coupling capacitor and the input resistance of the amplifier). This combination introduces a lower cutoff frequency for our amplifier which is the same as the cutoff frequency of the highpass filter: ω l = 2π f l = 1 i c Lastly, our small signal model is a lowfrequency model. As such, our analysis indicates that the amplifier has no upper cutoff frequency (which is not true). At high frequencies, the capacitance between,, layers become important and a highfrequency smallsignal model for JT should be used for analysis. You will see these models in upper division courses. asically, these capacitances results in amplifier gain to drop at high frequencies. PSpice includes a highfrequency model for JT, so your simulation should show the upper cutoff frequency for JT amplifiers. I o Vo Z L ommon mitter Amplifier D analysis: ecall that an emitter resistor is necessary to provide stability of the bias point. As such, the circuit configuration as is shown has as a poor bias. We need to include for good biasing (D signals) and eliminate it for A signals. The solution to include an emitter resistance and use a bypass capacitor to short it out for A signals as is shown. c V Poor ias c V b Good ias using a by pass capacitor For this new circuit and with the capacitors open circuit, this circuit is the same as our good biasing circuit of page 91. The bias point currents and voltages can be found using procedure of pages L Lecture Notes, Spring
6 A analysis: To start the analysis, we kill all D sources, combine and into and replace the JT with its small signal model. We see that emitter is now common between input and output A signals (thus, common emitter amplifier. Analysis of this circuit is straightforward. xamination of the circuit shows that: = r π i = ( c r o ) β i A v = β r π ( c r o ) β r π c = c r e c i β i r r π o i = r π o = r o The negative sign in A ndicates 180 phase shift between input and output. The circuit has a large voltage gain but has a medium value for input resistance. As with the emitter follower circuit, the load can be configured in two ways: 1) c is the load. Then o = r o and the circuit has a reasonable current gain. 2) Load is placed in parallel to c. In this case, we need to ensure that L c. Little current will flow in L and o and A i values are of not much use. Lower cutoff frequency: oth the coupling and bypass capacitors contribute to setting the lower cutoff frequency for this amplifier, both act as a lowpass filter with: ω l (coupling) = 2π f l = 1 i c ω l (bypass) = 2π f l = 1 b o where (r e β ) In the case when these two frequencies are far apart, the cutoff frequency of the amplifier is set by the larger cutoff frequency. i.e., ω l (bypass) ω l (coupling) ω l = 2π f l = 1 i c ω l (coupling) ω l (bypass) ω l = 2π f l = 1 b When the two frequencies are close to each other, there is no exact analytical formulas, the cutoff frequency should be found from simulations. An approximate formula for the cutoff frequency (accurate within a factor of two and exact at the limits) is: ω l = 2π f l = 1 i c 1 b 60L Lecture Notes, Spring
7 ommon mitter Amplifier with mitter resistance A problem with the common emitter amplifier is that its gain depend on JT parameters A v (β/r π ) c. Some form of feedback is necessary to ensure stable gain for this amplifier. One way to achieve this is to add an emitter resistance. ecall impact of negative feedback on OpAmp circuits: we traded gain for stability of the output. Same principles apply here. c V D analysis: With the capacitors open circuit, this circuit is the same as our good biasing circuit of page 91. The bias point currents and voltages can be found using procedure of pages A analysis: To start the analysis, we kill all D sources, combine and into and replace the JT with its small signal model. Analysis is straight forward using nodevoltage method. v r π v β i v r o = 0 v r o β i = 0 i = v r π (ontrolled source aux. q.) 1 v _ i r π β i i r o vo Substituting for i in the node equations and noting 1 β β, we get: v β v r π v r o v r o = 0 β v r π = 0 Above are two equations in two unknowns (v and ). Adding the two equation together we get v = ( / ) and substituting that in either equations we can find. Alternatively, we can find compact and simple solutions by noting that terms containing r o in the denominator are usually small as r o is quite large. In this case, the node equations simplify to (using r π /β = r e ): ( 1 v 1 ) = r e = r e (v ) = r e v = r e r e ( ) 1 r e = r e 60L Lecture Notes, Spring
8 Then, the voltage gain and input resistance can be easily calculated from the above equations: A v = = i = [β( r e )] r e As before the minus sign in A ndicates a 180 phase shift between input and output signals. Note the impact of negative feedback introduced by the emitter resistance. The voltage gain is independent of JT parameters and is set by and as r e (recall OpAmp inverting amplifier!). The input resistance is increased dramatically. To find o, we need to follow the procedure similar to that of page 107 to get: o = r o 1 1 β 1 r π r π r o 1 1 r π Assuming r o and r π, the above equation simplifies to: ( ) o r o 1 r e Lower cutoff frequency: The coupling capacitor together with the input resistance of the amplifer lead to a lower cutoff freqnecy for this amplifer (similar to emitter follower). The lower cutoff freqncy is geivn by: ω l = 2π f l = 1 i c 60L Lecture Notes, Spring
9 A Possible iasing Problem: The gain of the common emitter amplifier with the emitter resistance is approximately /. For cases when a high gain (gains larger than 510) is needed, may be become so small that the necessary good biasing condition, V = I > 1 V cannot be fulfilled. The solution is to use a bypass capacitor as is shown. The A signal sees an emitter resistance of 1 while for D signal the emitter resistance is the larger value of = 1 2. Obviously formulas for common emitter amplifier with emitter resistance can be applied here by replacing with 1 as in deriving the amplifier gain, and input and output impedances, we short the bypass capacitor so 2 is effectively removed from the circuit. c V 1 2 b The addition of bypass capacitor, however, modifies the lower cutoff frequency of the circuit. Similar to a regular common emitter amplifier with no emitter resistance, both the coupling and bypass capacitors contribute to setting the lower cutoff frequency for this amplifier. Similarly we find that an approximate formula for the cutoff frequency (accurate within a factor of two and exact at the limits) is: ω l = 2π f l = 1 i c 1 b where 2 (1 r e β ) 60L Lecture Notes, Spring
10 Summary of JT Amplifiers ommon ollector (mitter Follower): V A v = ( r o )(1 β) r π ( r o )(1 β) 1 c i = [r π ( r o )(1 β)] o = (r o ) r π (1 β)(r o ) r π r π β = r e 2π f l = 1 i c ommon mitter: V A v = β r π ( c r o ) β r π c = c r e i = r π o = r o 2π f l = 1 i c 1 b where (r e β ) c ommon mitter with mitter esistance: b c V = A v = r e i = [β( r e )] and o = r e ( r e 1 2π f l = 1 i c V ) A v = 1 r e 1 i = [β(1 r e )] o = r e ( r e 1 ) ω l = 2π f l = 1 i c 1 b = c 1 2 b where 2 (1 r e β ) If bias resistors are not present (e.g., bias with curent mirror), let. 60L Lecture Notes, Spring
11 xamples of Analysis and Design of JT Amplifiers xample 1: Find the bias point and A amplifier parameters of this circuit (Manufacturers spec sheets give: h fe = 200, h ie = 5 kω, h oe = 10 µs). r π = h ie = 5 kω r o = 1 h oe = 100 kω β = h fe = 200 r e = r π β = 25 Ω D analysis: 9 V eplace and with their Thevenin equivalent and proceed with D analysis (all D current and voltages are denoted by capital letters): 18k 0.47 µ F = 18 k 22 k = 9.9 kω V = = 4.95 V KVL: V = I V 10 3 I I = I 1 β = I ( ) = I 10 3 I = 4 ma I, KVL: I = I β V = V 10 3 I = 20 µa V = = 5 V D ias summary: I I = 4 ma, I = 20 µa, V = 5 V 22k V I V 1k 9 V I V 1k A analysis: The circuit is a common collector amplifier. Using the formulas in page 113, A v 1 i = 9.9 kω o r e = 25 Ω f l = ω l 2π = 1 2π c = 1 = 36 Hz 2π L Lecture Notes, Spring
12 xample 2: Find the bias point and A amplifier parameters of this circuit (Manufacturers spec sheets give: h fe = 200, h ie = 5 kω, h oe = 10 µs). r π = h ie = 5 kω r o = 1 h oe = 100 kω β = h fe = 200 r e = r π β = 25 Ω D analysis: 15 V eplace and with their Thevenin equivalent and proceed with D analysis (all D current and voltages are denoted by capital letters). Since all capacitors are replaced with open circuit, the emitter resistance for D analysis is = 510 Ω. 4.7 µ F 34 k 1 k = 5.9 k 34 k = 5.0 kω V = = 2.22 V k µ F KVL: V = I V 510I I = I 1 β = I ( ) = I 510 1k 15 V I = 3 ma I, KVL: I = I β = 15 µa V = 1000I V 510I V = 15 1, = 10.5 V D ias: I I = 3 ma, I = 15 µa, V = 10.5 V V I V I V = 510 A analysis: The circuit is a common collector amplifier with an emitter resistance. Note that the 240 Ω resistor is shorted out with the bypass capacitor. It only enters the formula for the lower cutoff frequency. Using the formulas in page 113: A v = 1 r e = i = 5.0 kω 1, = 3.39 ( ) o r e 1 = 1.2 M Ω r e = 2 (1 r e 5, 000 ) = 240 ( β 200 ) = 137 Ω f l = ω l 2π = 1 1 2π i c 2π = b 60L Lecture Notes, Spring
13 1 2π 5, = 31.5 Hz 6 2π L Lecture Notes, Spring
14 xample 3: Design a JT amplifier with a gain of 4 and a lower cutoff frequency of 100 Hz. The Q point parameters should be I = 3 ma and V = 7.5 V. (Manufacturers spec sheets give: β min = 100, β = 200, h ie = 5 kω, h oe = 10 µs). r π = h ie = 5 kω r o = 1 h oe = 100 kω r e = r π β = 25 Ω V The prototype of this circuit is a common emitter amplifier with an emitter resistance. Using formulas of page 113 (r e = r π /h fe = 25 Ω), c A v = r e = 4 The lower cutoff frequency will set the value of c. We start with the D bias: As V is not given, we need to choose it. To set the Qpoint in the middle of load line, set V = 2V = 15 V. Then, noting I I,: V = I V I = ( ) = 2.5 kω V i v _ V _ i v Values of and can be found from the above equation together with the A gain of the amplifier, A V = 4. Ignoring r e compared to (usually a good approximation), we get: = 4 4 = 2.5 kω = 500 Ω, = 2. kω ommercial values are = 510 Ω and = 2 kω. Use these commercial values for the rest of analysis. We need to check if V > 1 V, the condition for good biasing. V = I = = 1.5 > 1, it is OK (See next example for the case when V is smaller than 1 V). We now proceed to find and V. is found from good bias condition and V from a KVL in loop: (β 1) = 0.1(β min 1) = = 5.1 kω KVL: V = I V I V = = 2.28 V 60L Lecture Notes, Spring
15 ias resistors and are now found from and V : = = = 5 kω V V = = = can be found by dividing the two equations: = 33 kω. is found from the equation for V to be = 5.9 kω. ommercial values are = 33 kω and = 6.2 kω. Lastly, we have to find the value of the coupling capacitor: ω l = 1 i c = 2π 100 Using i = 5.1 kω, we find c = F or a commercial values of c = 300 nf. So, are design values are: = 33 kω, = 6.2 kω, = 510 Ω, = 2 kω. and c = 300 nf. xample 4: Design a JT amplifier with a gain of 10 and a lower cutoff frequency of 100 Hz. The Q point parameters should be I = 3 ma and V = 7.5 V. A power supply of 15 V is available. Manufacturers spec sheets give: β min = 100, h fe = 200, r π = 5 kω, h oe = 10 µs. r π = h ie = 5 kω r o = 1 h oe = 100 kω r e = r π β = 25 Ω V The prototype of this circuit is a common emitter amplifier with an emitter resistance. Using formulas of page 113: c A v = r e = 10 The lower cutoff frequency will set the value of c. We start with the D bias: As the power supply voltage is given, we set V = 15 V. Then, noting I I,: V = I V I = ( ) = 2.5 kω 60L Lecture Notes, Spring
16 Values of and can be found from the above equation together with the A gain of the amplifier A V = 10. Ignoring r e compared to (usually a good approximation), we get: = = 2.5 kω = 227 Ω, = 2.27 kω We need to check if V > 1 V which is the condition for good biasing: V = I = = 0.69 < 1. Therefore, we need to use a bypass capacitor and modify our circuits as is shown. For D analysis, the emitter resistance is 1 2 while for A analysis, the emitter resistance will be 1. Therefore: c V D ias: 1 2 = 2.5 kω 1 A gain: A v = 1 = 10 2 b Above are two equations in three unknowns. A third equation is derived by setting V = 1 V to minimize the value of 1 2. V V = (1 2 )I = = Now, solving for, 1, and 2, we find = 2.2 kω, 1 = 220 Ω, and 2 = 110 Ω (All commercial values). We can now proceed to find and V : V i i v v 1 2 (β 1)(1 2 ) = 0.1(β min 1)(1 2 ) = = 3.3 kω KVL: V = I V I V = = 1.7 V ias resistors and are now found from and V : = = = 3.3 kω V V = = 1 15 = L Lecture Notes, Spring
17 can be found by dividing the two equations: = 50 kω and is found from the equation for V to be = 3.6k Ω. ommercial values are = 51 kω and = 3.6k Ω Lastly, we have to find the value of the coupling and bypass capacitors: = 2 (1 r e 3, 300 ) = 110 ( β 200 ) = 77.5 Ω i = 3.3 kω ω l = 1 1 i c = 2π 100 b This is one equation in two unknown ( c and ) so one can be chosen freely. Typically b c as i. This means that unless we choose c to be very small, the cutoff frequency is set by the bypass capacitor. The usual approach is the choose b based on the cutoff frequency of the amplifier and choose c such that cutoff frequency of the i c filter is at least a factor of ten lower than that of the bypass capacitor. Note that in this case, our formula for the cutoff frequency is quite accurate (see discussion in page 109) and is ω l 1 b = 2π 100 This gives b = 20 µf. Then, setting 1 1 i c b 1 1 = 0.1 i c b i c = 10 b c = = 4.7 µf So, are design values are: = 50 kω, = 3.6 kω, 1 = 220 Ω, 2 = 110 Ω, = 2.2 kω, b = 20 µf, and c = 4.7 µf. An alternative approach is to choose b (or c ) and compute the value of the other from the formula for the cutoff frequency. For example, if we choose b = 47 µf, we find c = 0.86 µf. 60L Lecture Notes, Spring
18 xample 5: Find the bias point and A amplifier parameters of this circuit (Manufacturers spec sheets give: β = 200, r π = 5 kω, r o = 100 kω). This is a twostage amplifier. The first stage (Tr1) is a common emitter amplifier and the second stage (Tr2) is an emitter follower. The two stages are coupled by a coupling capacitor (0.47 µf). D analysis: When we replace the coupling capacitors with open circuits, we see the that bias circuits for the two transistors are independent of each other. ach bias circuit can be solved independently. 33k 4.7 µ F 2k Tr1 6.2k V 0.47 µ F For Tr1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and proceed with D analysis: 18k 22k Tr2 1k = 6.2 k 33 k = 5.22 kω and V 1 = = 2.37 V KVL: V 1 = I 1 V I 1 I 1 = I 1 1 β = I 1 ( ) = I I 1 = 3.17 ma I 1, KVL: I 1 = I 1 β = 16 µa V = I 1 V 1 500I 1 V 1 = = 7.1 V D ias summary for Tr1: I 1 I 1 = 3.17 ma, I 1 = 16 µa, V 1 = 7.1 V Following similar procedure for Tr2, we get: = 18 k 22 k = 9.9 kω and V 2 = = 8.25 V KVL: V 2 = I 2 V I 2 I 2 = I 2 1 β = I 2 ( ) = I L Lecture Notes, Spring
19 I 2 = 7.2 ma I 2, KVL: I 2 = I 2 β V = V I 2 = 36 µa V 2 = = 7.8 V D ias summary for T2: I 2 I 2 = 7.2 ma, I 2 = 36 µa, V 2 = 7.8 V A analysis: We start with the emitter follower circuit (Tr2) as the input resistance of this circuit will appear as the load for the common emitter amplifier (Tr1). Using the formulas in page 113: A v2 1 i2 = 9.9 kω f l2 = ω l2 2π = 1 2π c2 = 1 = 34 Hz 2π Since i2 = 9.9 kω is NOT much larger than the collector resistor of common emitter amplifier (Tr1), it will affect the first circuit. Following discussion in pages 106 and 111, the effect of this load can be taken into by replacing in common emitter amplifiers formulas with = L = i2 = 2 k 9.9 kω = 1.66 kω. A v1 = 1.66k 500 = 3.3 i1 = 5.22 kω f l1 = ω l1 2π = 1 2π c1 = 1 = 6.5 Hz 2π The overall gain of the twostage amplifier is then A v = A v1 A v2 = 3.3. The input resistance of the twostage amplifier is the input resistance of the firststage (Tr1), i = 9.9 kω. To find the lower cutoff frequency of the twostage amplifier, we note that: A v1 (jω) = A v1 1 jω l1 /ω and A v2 (jω) = A v2 1 jω l2 /ω A v (jω) = A v1 (jω) A v2 (jω) = A v1 A v2 (1 jω l1 /ω)(1 jω l2 /ω) From above, it is clear that the maximum value of A v (jω) is A v1 A v2 and the cutoff frequency, ω l can be found from A v (jω = ω l ) = A v1 A v2 / 2 (similar to procedure we used for filters). For the circuit above, since ω l2 ω l1 the lower cutoff frequency would be very close to ω l2. So, the lowercutoff frequency of this amplifier is 34 Hz. 60L Lecture Notes, Spring
20 xample 6: Find the bias point and A amplifier parameters of this circuit (Manufacturers spec sheets give: β = 200, r π = 5 kω, r o = 100 kω). This is a twostage amplifier. The first stage (Tr1) is a common emitter amplifier and the second stage (Tr2) is an emitter follower. The circuit is similar to the twostage amplifier of xample 5. The only difference is that Tr2 is directly biased from Tr1 and there is no coupling capacitor between the two stages. This approach has its own advantages and disadvantages that are discussed at the end of this example. 2k I 1 33k I µ F I 1 Tr1 6.2k 500 V 2 15 V Tr2 1k D analysis: Since the base current in JTs are typically much smaller that the collector current, we start by assuming I 1 I 2. In this case, I 1 = I 1 I 2 I 1 I 1 (the bias current I 2 has no effect on bias parameters of Tr1). This assumption simplifies the analysis considerably and we will check the validity of this assumption later. For Tr1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and proceed with D analysis: = 6.2 k 33 k = 5.22 kω and V 1 = = 2.37 V KVL: V 1 = I 1 V I 1 I 1 = I 1 1 β = I 1 ( ) = I I 1 = 3.17 ma I 1, KVL: I 1 = I 1 β = 16 µa V = I 1 V 1 500I 1 V 1 = = 7.1 V D ias summary for Tr1: I 1 I 1 = 3.17 ma, I 1 = 16 µa, V 1 = 7.1 V To find the bias point of T2, we note: V 2 = V I 1 = = 8.68 V 60L Lecture Notes, Spring
21 KVL: V 2 = V I = 10 3 I 2 I 2 = 8.0 ma I 2, KVL: V = V I 2 I 2 = I 2 β = 40 µa V 2 = = 7.0 V D ias summary for T2: I 2 I 2 = 8.0 ma, I 2 = 40 µa, V 2 = 7.0 V We now check our assumption of I 1 I 2. We find I 1 = 3.17 ma I 2 = 41 µa. So, our assumption was justified. It should be noted that this bias arrangement is also stable to variation in transistor β. The bias resistors in the first stage will ensure that I 1 ( I 1 ) and V 1 is stable to variation of T1 β. Since V 2 = V 1 1 I 1, V 2 will also be stable to variation in transistor β. Finally, V 2 = V 2 2 I 2. Thus, I 2 ( I 2 ) will also be stable (and V 2 because of KVL). A analysis: As in xample 5, we start with the emitter follower circuit (Tr2) as the input resistance of this circuit will appear as the load for the common emitter amplifier (Tr1). Using the formulas in page 113 and noting that this amplifier does not have bias resistors ( ): A v2 1 i2 = r π ( r o )(1 β) = = kω Note that because of the absence of the bias resistors, the input resistance of the circuit is very large, and because of the absence of the coupling capacitors, there is no lower cutoff frequency for this stage. Since i2 = kω is much larger than the collector resistor of common emitter amplifier (Tr1), it will NOT affect the first circuit. The parameters of the firststage common emitter amplifier can be found using formulas of page 113. A v1 2, 000 = 500 = 4 i1 = 5.22 kω f l1 = ω l1 2π = 1 2π c1 = 1 = 6.5 Hz 2π L Lecture Notes, Spring
22 The overall gain of the twostage amplifier is then A v = A v1 A v2 = 4. The input resistance of the twostage amplifier is the input resistance of the firststage (Tr1), i = 9.9 kω. The find the lower cutoff frequency of the twostage amplifier is 6.5 Hz. The twostage amplifier of xample 6 has many advantages over that of xample 5. It has three less elements. ecause of the absence of bias resistors, the secondstage does not load the first stage and the overall gain is higher. Also because of the absence of a coupling capacitor between the twostages, the overall cutoff frequency of the circuit is lower. Some of these issues can be resolved by design, e.g., use a large capacitor for coupling the two stages, use a large 2, etc.. The drawback of the xample 6 circuit is that the bias circuit is more complicated and harder to design. In general, the saturation voltage for the amplifer is smaller compared to twostage amplifier with a coupling capcitor between staes (such in xample 5). 60L Lecture Notes, Spring
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