Hardware/Software Codesign

Transcription

1 Hardware/Software Codesign. Review. Allocation, Binding and Scheduling Marco Platzner Lothar Thiele by the authors Synthesis Behavior Structure Synthesis Tasks ΠAllocation: ΠBinding: ΠScheduling: selection of components assignment of functions to components determination of the execution order Page

2 Design of Embedded Processors x := a*b -(c+d)*e machine code Allocation Πregisters, ALU, etc., given Binding Πregister binding, instruction binding Scheduling Πinstruction sequence TMS0C5 System design Given: algorithms mappings architectures I I K Goal: schedule mapping architecture interfaces '0$ &, Objectives: cost, latency, power consumption, Page

3 Allocation on the System Level Processors, dedicated Hardware Memory, I/O Interconnects MIPS DSP Mem Mem 5 Binding on the System Level A B C D MIPS DSP Mem E Mem Page

4 Scheduling on the System Level DSP MIPS A DSP A B B MIPS C MIPS C D D E E time time Basic Model Problem Graph Problem graph G P (V P,E P ): 5 Interpretation: V P consists of functional nodes V f P (task, procedure) and communication nodes V c P. E P represent data dependencies 8 Page

5 Basic model architecture graph Architecture graph G A (V A,E A ): HWM HWM shared bus HWM Architecture PTP bus shared bus HWM Architecture graph PTP bus V A consists of functionalresources V f A (, ) and bus resources V c A. These components are potentially allocatable. E A modeldirected communication. 9 Basic model specification graph Definition: Aspecification graph is a graph G S =(V S,E S ) consisting of a problem graph G P, an architecture graph G A, and edges E M.In particular, V S =V P V A, E S =E P E A E M 5 G P E M G A SB HWM PTP HWM 0 Page 5

6 Basic model - synthesis Three main tasks of synthesis: Allocation α is a subset of V A. Binding β is a subset of E M, i.e., a mapping of functional nodes of V P onto resource nodes of V A. Schedule τ is a function that assigns a number (start time) to each functionalnode. Basic model - implementation 0 Definition: Given a specification graph G S an implementation is a triple (α,β,τ), where α is a feasible allocation, β is a feasible binding, and τ is a schedule. 9 0 τ α β HWM shared bus SB HWM PTP bus HWM Page

7 ABS - example S() = BUS S() = 5 S() = BUS DSP S() = 5 DSP 5 BUS S(5) = 5 S() = 9 5 BUS S() = G V problem graph M mapping set G S B A A architecture schedule binding allocation graph Optimization with conflicting goals Multiobjective optimization: Find a set of optimal trade-offs ΠExample: computer design performance power dis play weight s iz e cos t conflicts trade-offs Page

8 Dominance, Pareto Points Definition: A (design) point J k is dominated by J i, if J i is Πbetter or equal than J k in all criteria and Πbetter in at least one criterion. Ji f J k Definition: A point is Pareto-optimal or a Pareto-point, if it is not dominated. 5 Dominance, Pareto Points execution time 5 cost Page 8

9 Design space exploration tool Solution INM OUT M FM SBS 8 Page 9

10 Solution INM OUT M DPF M HC DCT M BMM SAM SBF 9 Page 0