2.3 Minimisation Techniques For Digital Logic Design

Transcription

1 Combinational Logic:- Minimisation Techniques Minimisation Techniques For Digital Logic Design Definition 2.4: Two logical products, and, are logically adjacent iff when has the literals then has the literals (or vice versa). That is, and have identical literals everywhere except for the literal. When and are logically adjacent, as in Definition 2.4 above, we can apply the absorption law to + and result in + where =. So, applying the idempotency law we get. As an illustration consider the products and. These are logically adjacent since they both have identical literals and and differ only on their third literal. The first product has, as its third literal, while the second product has it as. So, given the expression +, one can, in essence, factor out (Observation 1.1) to get. But. So, the result is just. This factorisation is a short cut for applying the laws: Absorption then Idempotency in order! The reason being that: (Absorption). B + B = B (Idempotency). Therefore, The Algebraic Minimisation Technique In order to easily reduce a somewhat more complex Boolean expression to a relatively simpler one, one can execute the following algorithm: 0. Put the given Boolean expression in SSOP form. 1. Group the resulting products into suitable logically adjacent pairs. If there is more than one way of grouping the logically adjacent pairs then permute the groupings and select the ordering that results in the maximum number of pairs. This process may require that one or more duplicate minterms (products) be added to the expression. 2. Apply the following laws in order: a) Absorption Law to each logically adjacent pair then b) (If possible) Idempotency Law to each result. 3. Repeat step 1 to 2 until no further progress. 4. At the end the resulting expression will be the minimal one. Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -38-

2 Combinational Logic:- Minimisation Techniques -39- Example 2.6: Minimise Solution: We realise that the expression is already in SSOP form. So, we proceed by forming logically adjacent pairs as follows: = Absorption Law = Idempotency Law = Idempotency Law = Logically adjacent pairs = Absorption Law = Idempotency Law Logically adjacent pairs The algebraic minimisation algorithm makes it sounds like it is very easy to carry out this minimisation process. However, this is not the case. Step 1 of the algorithm is the catch! It is possible that one may never be able to group the products into suitable logically adjacent pairs. This step depends largely on individual's ingenuity and logic skills The Karnaugh Map Minimisation Technique Introduction The Karnaugh Map, usually referred to as the K-Map, is a graphical minimisation tool which is very handy when minimising functions of 4 variables or less. The map is organised in such a way that all the cells in the map/table are logically adjacent to one another. That is, physically adjacent cells (i.e table cells sharing the same edge) are made to hold logically adjacent (binary) numbers. The following are typical K-Maps (for functions of 2, 3 and 4 variables): 1. Functions of 2 variables, f(a, B) A B Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -39-

3 Combinational Logic:- Minimisation Techniques AB We realise that each of the cells are logically adjacent to one another as follows: Row Adjacent Pair Column Adjacent Pair 1 and 1 and 2 and AB 2 and AB 2. Functions of 3 variables, f(a, B, C) AB C Functions of 4 variables, f(a, B, C, D) AB CD Because of the manner in which logically adjacency is made to tally with physical adjacency, it is clear therefore that a single 2-dimensional K-map can at most represent a function of 4 variables - each table cell only has 4 sides! When the number of variables increases beyond 4, 2 or more K-maps, each of 4 or less variables, are used combined to find logical adjacency or a 3-dimensional table employed. Consider a single 2-dimensional K-Map. The reader should observe that the entries in the K-Map are minterms. Therefore, in order to plot a Boolean function f on a K-Map one needs to first of all express f in SSOP form and plot f as follows: for any minterm where f = 1, write a 1 in the corresponding cell on the K-Map. For any minterm where f = 0, write a 0 in the corresponding cell on the K-Map. Now what we have is a K-Map of 0's and 1's. We minimise f using the Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -40-

4 Combinational Logic:- Minimisation Techniques -41- following algorithm. 0. Encircle (or shade) all the consecutive 1's (in the rows and columns) in such a way as to form the largest group of 1's forming a number which is a power of 2. This is your largest number of logically adjacent pairs of the given f expression. NB: A cell can be encircled as many times as possible into other groupings of 1's (i.e application of the Idempotency Law - A + A = A). 1. Now, apply the Absorption and Idempotency laws as follows: 1.1 Observe the headings of the variables (both for the rows and the columns). 1.2 If from one cell to another next cell, a variable changes from 1 to 0 ( or from 0 to 1) within the same encircled group, such a variable is dropped from the minterm. The resultant product for the whole group will be only those variables whose headings remain constant throughout the entire group. 1.3 Repeat 1.2 for all the encircled groups. 2. We now write f as the logical sum of all the resultant products (from each encircled group). This is the minimal expression for f. Example 2.7: Minimise the function of Example 2.6 using a K-Map. Solution: The function is: = We plot f on a 3-variable K-Map as follows: We now shade all logically adjacent cells (i.e consecutive 1's in rows and columns) as follows: Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -41-

5 Combinational Logic:- Minimisation Techniques -42- It should be easy for the reader to see that the right edge is logically adjacent to the left edge and the upper row is logically adjacent to the lower row. We now begin the process of omitting variables whose values are changing within the encircled groups as follows: For the group we realise that from the first column to the second one, variable same time, from the first row to the second one, variable changes from 0 to 1. At the changes from 0 to 1. Therefore, we omit and from the minterm and our resultant product becomes just (since remains constantly low (i.e 0) throughout the entire group). For the group we realise that from the left edge to the right one, variable changes from 0 to 1. At the same time, from the first row to the second one, variable changes from 0 to 1. So, omitting and from the minterm we get our resultant product as just (since remains constantly low throughout the entire group). Therefore, the minimal expression for is given by (as shown in Example 2.6). Example 2.8: Design a minimal circuit for the 2-bit multiplier of Example 2.3. Solution: We plot the K-Map for each of the outputs as follows. We note that each, i = 0, 1, 2, 3 is a function of 4 variables,. So, Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -42-

6 Combinational Logic:- Minimisation Techniques -43- For, we have So, changes from 0 to 1 (from the first column to the second one) and changes from 0 to 1 (from the first row to the second one). Therefore,. For, we have Therefore, For we have, Thus, For we have, Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -43-

7 Combinational Logic:- Minimisation Techniques -44- Thus, Now, we construct the circuit subject to the same constraints as in Example 2.3. So, The reader should note that Proposition 2.1 gives us another way of expressing a Boolean expression. This is that, instead of using the usual variables in the expression, we can just write the binary value for each variable in the product as follows. For any Boolean variable A, if A appears in the expression we write 1 and if it is we write 0. For example, the function: = can be expressed as = Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -44-

8 Combinational Logic:- Minimisation Techniques -45- In fact, in our K-Map minimisation technique above, we have used this notation as if we had already agreed upon it. This notation is commonly used in digital logic design. However, if any confusion arises it is better to use the actual variables. We mentioned earlier on that the K-Map is useful for functions of 4 variables and less. When variables increase it becomes impossible to represent the logically adjacent pairs on a single map. In this case, the technique employed is to increase the number of maps. But now, to find which cell is logically adjacent to which one becomes very difficult and therefore the K-Map is rendered useless. Alternatively, one can use a technique called variable entered K-Map Variable Entered (K-)Map -VEM A VEM is a K-Map in which the cell entries are allowed to be any arbitrary truth functions not necessarily the two truth value constants 0 and 1. Each cell entry function can further be reduced by either applying the algebraic techniques or further applications of (variable entered) K-Maps. For a VEM, when grouping logically adjacent cells or regions we group together cells that contain identical truth functions - identical in the sense of logic algebra. This means, for example, that if in one cell entry we have a truth function X and in the next logically adjacent cell we have another truth function Y - logically different, we cannot group the two cells together. For example, a cell entry containing logically adjacent to another cell containing cannot be grouped together since they contain two different truth functions. That is,. A VEM comes in handy when the number of variables are more than 4 (a de facto barrier for a 2-dimensional K-Map). Other than using multiple K-Maps, one can use VEMs iteratively on each cell entry functions to continuously reduce the number of variables in the resulting subexpressions. The following examples help illustrate the technique. Example 2.9: Using a VEM minimise the following function using a) a 4 variable VEM b) a 3 variable VEM Solution = a) Suppose we will enter into our cell entries a function of variable I. Then our VEM becomes Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -45-

9 Combinational Logic:- Minimisation Techniques -46- =. If the expression was further minimisable, then one could use any minimisation technique to reduce it further - this time around using the variables now that the variables have been eliminated from the resulting sub-expression. Of course, in this case the reader can see that is minimal so no further reduction will be possible. b) Let s suppose that we shall populate our cell entries with functions of then our VEM may look like: The reader will note that the cell entries are reducible functions and our table can actually be reduced to the following: = once more. Example 2.10: Minimise the function = Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -46-

10 Combinational Logic:- Minimisation Techniques -47- using a 2-variable VEM. Solution Suppose we use as our variable headings and the cell entries to be functions of, then our VEM could be: This is reducible to the following: The question is, is law we have minimal? The answer is, clearly not, since applying the distributive = = which is minimal. Alternatively, the reader might have wanted to check this function using a 2-variable K-Map as follows: First we write the expression in the usual SSOP form as: = = On a 2-variable K-Map this function plots as: which is minimal. Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -47-

11 Combinational Logic:- Minimisation Techniques -48- In the next section we discuss another minimisation technique which is of general applicability to any function with any number of variables The Quine-McCluskey Minimisation Technique Definition 2.5: Let f, g and h be any Boolean expressions. 1. g implies f (i.e g f) iff + f = If h = g + f and g f then h = f. That is, g (i.e the implicating expression) can be eliminated from the entire h expression. This is because if + f = 1 then g f. Thus, h = g + f h = f + f h = f (Idempotency Law). Definition 2.6: Let f be an n-ary Boolean function. A prime implicant P of f is a product term of m literals, m n, such that P f and, being any product term obtained by deleting a literal from P, does not imply f. Example 2.11: Let. a) Show that each of these product terms implies f. b) Determine the prime implicant. Solution: a) Let = x, = and =. Then f since + f = = 1. f since + f = = = = 1 f since + f = = = = 1 b) It should be clear from the above proceedings that is essential in the expression in order to Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -48-

12 Combinational Logic:- Minimisation Techniques -49- have any + f = 1, i = 1, 2, 3. It is trivial to see that one can delete either or or both from and still get f. In the same way, can be deleted from and still get f. However, if x is deleted from then none of the remaining products could ever imply f. Therefore, is the prime implicant of f. Prime implicants are essential in minimisation techniques. In fact, in all the minimisation techniques we have studied so far, we have always been trying to write the given function as a sum of its prime implicants. This procedure is now given a formal support by the following proposition which we state without proof. Proposition 2.2: Any minimal SOP form of a Boolean expression will always consist of a sum of prime implicants. We are now ready to present the Quine-McCluskey minimisation algorithm for producing a list of prime implicants from any given Boolean expression. 0. Express the given Boolean expression in SSOP form. 1. Form an initial table, say Table 1, of the equivalent binary products from the minterms as follows: 1.1 Group the products in increasing order of the number of 1's present (in the product) such that all the products with the least number of 1's will be in the first row. If there is some confusion, it is better to include an extra column of the corresponding minterm products. 1.2 What we now have is a table consisting of rows of groups of binary numbers such that R, 1 R - 1, R being the row count and the total number of rows for the current table, all the binary numbers in R have equal number of 1's, say B, and all the binary numbers in R + 1 have number of 1's bigger or equal to B + 1 (the number of 1's will be exactly B + 1 if the binary numbers in R + 1 are logically adjacent to the binary numbers in R). 1.3 Set Table = 1 (start with the initial table) 2. We apply the Absorption and Idempotency laws to each logically adjacent pair as follows: 2.1 Set R = 1 (Start with the first row) 2.2 NextTable = 0 (Assume no new table can be produced) 2.3 If R = then STOP (i.e there are no logically adjacent pairs). 2.4 Coalesce each number from row R with its logically adjacent counterpart in row R + 1 Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -49-

13 Combinational Logic:- Minimisation Techniques -50- and put a dash for the omitted position (i.e literal). Put the resultant (i.e the coalesced) product in row R of the new table, NextTable = Table + 1 (if it is not already there present). Mark this coalesced pair (if it is not already marked). NB: A number can be coalesced with as many logically adjacent numbers as there are possible. 2.5 Set R = R + 1 (move to the next row) Go To Step Set Table = Table + 1 (Assume there is a new table produced). If Table = NextTable then Go To Step 2. (i.e try to reduce any logically adjacent pairs in this newly produced table). In the end, the prime implicants for the given Boolean expression are all the unmarked products in all the tables. Example 2.12: Write the following function, using the Quine-McCluskey's minimisation technique, as a some of its prime implicants. Solution: = By the step 0 of the algorithm we produce the following table: Table 1 Row Binary Product Product Term Now, we begin coalescing logically adjacent pairs from row 1 and row 2 as follows: Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -50-

14 Combinational Logic:- Minimisation Techniques For the first row we coalesce 000 with each of the products in row 2 as follows: 000 can be coalesced with 001 to produce 00-. And we mark this pair. 000 can also be coalesced with 010 to form 0-0 and this pair is also marked. 000 with 100 produce -00 and this pair is also marked. Now, 00-, 0-0, -00 will be in row 1 of a new table - Table For row 2 and row 3 we have: 001 with 011 produces with 101 results in with 011 will produce with 101 will result in 10- Now, these reduced terms will be in row 2 of Table 2. So, the marked Table 1 and the new Table 2 are: Table 1 Row Binary Product Product Term Table 2 Row Binary Product Product Term Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -51-

15 Combinational Logic:- Minimisation Techniques -52- Again, by step 3 of the algorithm, we find that we have to try to reduce Table 2 to produce Table 3 as follows: We start with 00-. So, 00- with 01- produces 0-- (and we mark the pair). 00- with 10- produces -0- (and we mark the pair). Next we take 0-0. So, 0-0 with 0-1 produces 0-- (which we already have - so we don't include it in Table 3). We, however, mark this pair. Lastly, we pick -00. So, -00 with -01 produces -0-. We don't include this since we already have it from above. But, again we mark this pair. The marked Table 2 and the resulting Table 3 are as follows: Table 2 Row Binary Product Product Term Table 3 Row Binary Product Product Term We now realise that we can no longer reduce Table 3 since it has only one row. That is, when we set R = 1 in Step 2.1 of the algorithm then R = in Step 2.3 (of the algorithm) and we have to STOP. Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -52-

16 Combinational Logic:- Minimisation Techniques -53- Now, we look for any unmarked products from Table 1 to Table 3. We discover that all products are marked except those in Table 3. These are, therefore, our prime implicants. So, the reduced expression can be written as a sum of its prime implicants as: are now ready to present the final step (i.e algorithm) to find the minimal expression for the given Boolean function from the sum of its prime implicants. First we need some preliminary definitions. Definition 2.7: Let be a sum of prime implicants for a Boolean function f. 1. A non-essential prime implicant,, is the one that implies the sum of the other remaining prime implicants. That is,. 2. An essential prime implicant,, is the one that does not imply the logical sum of the remaining prime implicants. Definition 2.8: A non-redundant sum of products is a logical sum of prime implicants such that if any product is deleted from the expression the reduced (i.e the resulting) expression is no longer logically equal to the original Boolean expression. A non-redundant sum is the minimal expression for the given Boolean function. The non-redundant sum will always consist of all the essential (i.e core) prime implicants and possibly few non-essential prime implicants. The following algorithm will produce a non-redundant sum from a logical sum of prime implicants: 0. Form a prime implicant table against the minterms of the original Boolean expression. This table is of the form:. We Prime Implicants Minterms for the original Boolean expression... Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -53-

17 Combinational Logic:- Minimisation Techniques Now, mark each entry as follows: set i to be the row count for the prime implicants, 's. set j to be the column count for the minterms, 's. For i = 1 to n Do For j = 1 to k Do mark the entry if covers. (For example, 00-- covers the minterms: 0000, 0001, 0010 and 0011). 2. Produce an initial non-redundant sum, R, by adding all the essential prime implicants. An essential prime implicant,, is the prime implicant such that: a) there is a mark in entry, 1 j k and b) t, 1 t i-1 and i+1 t n, entry is not marked. That is, there is only one mark in column j. 3. Strike out all the essential prime implicant rows from the table. The rows left, if any, are the rows for the non-essential prime implicants. 4. Add to R the non-essential prime implicant,, t = 1, 2, 3,..., n, if covers one or more minterms not (already) covered by R. If there are more than one such 's, choose the one with the minimum number of literals. 5. Repeat step 3 until R covers all the minterms (possibly leaving some non-essential prime implicants). Example 2.13: Is the prime implicant sum function of Example 2.6? (Example 2.10) the minimal Boolean expression for the Solution: First, we form the prime implicant table as follows: Prime Implicants Minterms for the original Boolean expression Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -54-

18 Combinational Logic:- Minimisation Techniques -55- Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page We now execute step 1 of the algorithm and the above table becomes: Prime Implicants Minterms for the original Boolean expression So, by step 2 of the algorithm, we realise that is an essential prime implicant by observing column 2. (One could have reached the same conclusion by observing column 6). Similarly, is an essential prime implicant (by observing column 4). Therefore, our (initial) non-redundant sum is:. Striking out these two rows (step 3) leaves no row in the table. Finally, by step 4 (and step 5) of the algorithm there are no non-essential prime implicants to add to our non-redundant sum above. Therefore, is the minimal Boolean expression for the given function (cf Example 2.6). Example 2.14: The function is given. Use the Quine-McCluskey's technique to a) get its prime implicants b) find its minimal (i.e non-redundant sum) expression. Solution: a) First, we form the table Table 1 Row Binary Product Product Term 1 001

19 Combinational Logic:- Minimisation Techniques Coalescing, we produce the table Table 2 Row Binary Product Product Term That is, 0-1 is the result of coalescing the pair (001, 011). -11 is the result of coalescing the pair (110, 111). 11- is the result of coalescing the pair (011, 111). Therefore, all these pairs are marked. We now realise that we can no longer reduce table 2. So, the prime implicants are, and. b) Is + + a minimal expression? We begin by building the prime implicant table vs function minterms and mark it appropriately as follows: Prime Implicants Minterms for the original Boolean expression We then discover (by looking at column 1) that is an essential prime implicant. Again, (by observing column 3) is also an essential prime implicant. The only non-essential prime implicant is. So, by step 2 of the algorithm, our initial non-redundant sum is given by +. Now, by step 3 (and step 4) of the algorithm can we add to our non-redundant sum? The Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -56-

20 Combinational Logic:- Minimisation Techniques -57- answer should be no since our non-redundant sum covers every minterm. For example, covers the minterms and. However, is covered by and is covered by Don't Care States Depending on the problem at hand (i.e its interpretation), we may find that certain inputs, although part of the possible input combinations, will never occur. Such inputs/states are normally referred to as the don't care states. The idea is that when minimising the function we can use these states to our advantage. That is, we could make the function assume 1 at a don't care state if this would help in reducing the function expression, otherwise we could let the function take the value 0. Usually, in a minimisation table, a don't care state would be represented by a d or an x. Caution should be exercised when attempting to use don't care states. One should grasp the interpretation of the problem very well in order to avoid designing a wrong circuit - having assumed wrongly the corresponding don't care situations. Example 2.15: Construct a minimal circuit that produces a 1 whenever a binary coded decimal (BCD) digit appears even and 0 if it is odd. Solution: In BCD, each digit is given its binary representation. For example, 15 will be written as , whereas in pure binary 15 is Therefore, a BCD digit has its corresponding binary representation for the (decimal) numbers: 0, 1, 2,..., 9. Observe, therefore, that there is no BCD digit representation for the binary numbers: 1010 through Since 9, in binary, is 1001, we have 4 binary inputs. Let us call them ABCD (A being the MSB and D the LSB). So, our function truth table then follows: BCD Digit Function Output ABCD 0000 (even) (odd) (even) (odd) (even) (odd) 0 Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -57-

21 Combinational Logic:- Minimisation Techniques (even) (odd) (even) (odd) (never occurs) d 1011 (never occurs) d 1100 (never occurs) d 1101 (never occurs) d 1110 (never occurs) d 1111 (never occurs) d We will plot this function on a K-Map to see if we could minimise it. We use the K-Map here because it surpasses the other methods in helping in the best use of the don't care states. The encircled region is from the top edge to the bottom edge. From the top edge to the bottom one, we find C changing from 0 to 1 (so we will drop it from our resulting product term). From column 1 to column 2, B changes from 0 to 1. From column 2 to column 3, A changes from 0 to 1. Therefore, our resulting product is! The reader should observe that, had we not let the function assume 1 at a "d", our K-Map would look like: which results in the expression:! Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -58-

22 Combinational Logic:- Minimisation Techniques -59- Example 2.16: Design a logic circuit for a signed real division with the following specifications: 1. The inputs are two signed integer numbers X and Y (written as and respectively) which are 2-bits each - excluding the sign bit ( ), where indicates the sign of number M. The numbers are in sign and magnitude notation. 2. The output is a real number, again in sign and magnitude notation, whose magnitude is 2 integer positions and 2 decimal places, as in the following block diagram: Solution: First we start with the truth table analysis. We start by analysing the truth table for the sign bit output. We know that, for any division of two numbers - sign and magnitude notation, if we have unlike signs then the result will be negative. When the signs are the same then the answer will be positive. So, Inputs Output Sign of X Sign of Y Sign of X Y Thus At this juncture we would like to introduce a new logic gate symbol. Recall that in chapter 1, exercise 4, we defined the Exclusive OR function as: A B =. The logic gate for this function is: Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -59-

23 Combinational Logic:- Minimisation Techniques -60- This is called an EXOR gate. An EXOR function, though not adequate (like NOR and NAND), can be used in many applications. Because of this, EXOR gates can be found in IC's. The EXOR function has the property that, for any Boolean variables A, B and C: (A B) C = A (B C) = A B C So, our division sign function is just one EXOR gate: We now analyse the division computation, considering only the number magnitudes. The reader will note that without our sign analysis above, the truth table will be enormous since we will have a total of six bits to consider (i.e 3 bits for each number) resulting in rows! The sign analysis has cut that number down to just 16 rows (i.e only 4 bits to consider - 2 bits from each X and Y). The truth table is as follows: Inputs Outputs X Y error flag d d. d d d d. d d d d. d d d d. d d Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -60-

24 Combinational Logic:- Minimisation Techniques The reader will note that the truth table analysis reveals that there is an extra output called which was not so explicit in the problem specification. The purpose of this extra output is to signal the time when the denominator is 0, in which case the division result is indeterminate. We have represented this situation as a don t care state - since the result is not meant to be used in this case. For all intents and purposes, it is just junk! The output equations then follow: Although we could just hard wire the circuit straight from the equations above, we would like to minimise it - just to make it handy. We pick the K-Map minimisation technique since it is easy because it is graphical and we will easily see the don t care states and use them to our advantage. So, Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -61-

25 Combinational Logic:- Minimisation Techniques -62- So the complete circuit may look like: Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -62-

26 Combinational Logic:- Minimisation Techniques Exercises 1. Write the following Boolean functions i) f(a, B, C, D) = A + B ii) f(a, B, C) = iii) f(a, B, C, D, E) = iv) f(a, B, C, D) = A in both the SSOP and SPOS forms 2. Minimise the following Boolean functions using both the K-Map and the Quine-McCluskey's minimisation techniques. a) f(x, y, z) = b) f(w, x, y, z) = + 3. Design a minimal 2-bit real number multiplication function, subject to the following specification: The circuit accepts, as input, two numbers X and Y. Each number has, excluding the sign bit, 2 bits before the decimal and 2 bits after the decimal. The output has 4 bits before Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -63-

27 Combinational Logic:- Minimisation Techniques -64- the decimal and 6 bits after the decimal. Both the inputs and output are in sign and magnitude notation. 4. Design a minimal 2-bit integer summation in a 1's complement. The inputs are two integers X and Y, 3-bits each - the MSB being the sign bit. 5. Modify Exercise 4 above so that the circuit now operates in 2's complement. 6. A Liquid Crystal Display (LCD) has seven (7) segments numbered as shown below. These are illuminated according to the number to be displayed. For example, 11 (3 decimal) will illuminate the bars a, b c, d, g and both e and f will receive a low signal as shown below. Design the minimal interface logic circuit for all the decimal digits Introduction to Structured Digital Logic Design for Computer Science Mphaka M. Page -64-