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1 System Modelingg Models of Computation and their Applications Axel Jantsch Laboratory for Electronics and Computer Systems (LECS) Royal Institute of Technology, Stockholm, Sweden February 4, 2005
2 System Modeling, JanFeb 2005, Kista Introduction 1 Contents Introduction Finite State Machines Petri Nets The Untimed Model of Computation The Synchronous Model of Computation The Timed Model of Computation Integration of Different Computational Models Tightly Coupled Process Networks Nondeterminism and Probability Applications
3 System Modeling, JanFeb 2005, Kista Introduction 2 Introduction Motivation System and Model Properties Rugby Meta Model Case Study: A Design Project
4 System Modeling, JanFeb 2005, Kista Introduction 3 Why do we need models? To perform various design tasks! Performance modeling Functional modeling and specification Design and synthesis Validation and verification Test vector generation Test coverage analysis Architecture evaluation and mapping Technology mapping Placement and routing
5 System Modeling, JanFeb 2005, Kista Introduction 4 What is a Model? Model: A model is a simplification of another entity, which can be a physical thing or another model. The model contains exactly those characteristics and properties of the modeled entity which are relevant for a given task. A model is minimal with respect to a task, if it does not contain any other characteristics than those relevant for the task. A model relates to an entity A model is a simplification of that entity A model is related to a task and an objective A model may relate to a not yet existing entity
6 System Modeling, JanFeb 2005, Kista Introduction 5 Properties of Models Inherent property: The property is inherent in every model. E.g. the finite state space of a finite state machine model. Static property: The property can be statically evaluated. E.g. the required memory of a finite state machine model. Dynamic property: The property can only be dynamically evaluated. E.g. the required memory of a C program.
7 System Modeling, JanFeb 2005, Kista Introduction 6 Heterogeneous Models are Necessary A system consists of different parts. E.g. data flow and control flow dominated parts. Different objectives apply for different parts. E.g. the system and its environment. Different parts are developed by different people and tools. E.g. HW and SW.
8 System Modeling, JanFeb 2005, Kista Introduction 7 What is a System? A system is an aggregation or assemblage of things so combined by nature or man as to form an integral or complex whole [Encyclopedia America] a regularly interacting or independent group of items forming a unified whole [Webster s Dictionary] a combination of components that act together to perform a function not possible with any of the individual parts [IEEE Standard Dictionary of Electrical and Electronic Terms]
9 System Modeling, JanFeb 2005, Kista Introduction 8 The InputOutput Modeling Process u(t) = u 1(t). u p (t) y(t) = y 1(t). y m (t) y 1 (t) = f 1 (u 1 (t),..., u p (t)). y m (t) = f m (u 1 (t),..., u p (t)) y(t) = f( u(t)) = f 1(u 1 (t),..., u p (t)). f m (u 1 (t),..., u p (t))
10 System Modeling, JanFeb 2005, Kista Introduction 9 A Mathematical Model of a Real System inputs outputs System u(t) y = f( u) Model
11 System Modeling, JanFeb 2005, Kista Introduction 10 Example Temperature Controller temperature sensor [0V, 5V] temperature controller [ 5V, +5V] heater/ cooler [0, 50 ] temperature controller [ 1, 1] TC1 y(t) = R T u(t) 50 [0V, 5V] temperature controller TC2 [ 5V, +5V] y(t) = R V u(t) [0, 255] temperature controller TC3 [ 127, +127] y(t) = R N u(t) 4
12 System Modeling, JanFeb 2005, Kista Introduction 11 Static and Dynamic Systems Definition: A static system is one where the output y(t) is independent of past values of the input u(t ), t < t for all t Definition: A dynamic system is one where the output y(t) depends on the current input value u(t) and on at least another input value u(t ) with t < t, y(t) = f(u(t), u(t )).
13 System Modeling, JanFeb 2005, Kista Introduction 12 TimeVarying and TimeInvariant Systems Definition: A model M with y(t) = f( u(t)) is timeinvariant if, supplied with input variables u (t) = u(t + τ), it defines output variables y (t) = f( u (t)) = y(t + τ) for any τ. Definition: In contrast, a timevarying model is one for which this property does not hold, i.e. where the output function explicitly depends on t: y(t) = f( u(t), t).
14 System Modeling, JanFeb 2005, Kista Introduction 13 A TimeInvariant System u(t) y(t) = f(u(t)) t t u (t) = u(t + τ) y (t) = f(u (t)) = y(t + τ) τ t τ t
15 System Modeling, JanFeb 2005, Kista Introduction 14 The Concept of State Definition: The state of a system at time t 0 is the information required such that the output y(t) for all t t 0 is uniquely determined by this information and the inputs u(t), t t 0. The state of a system at time t 0 is called the initial state ( x 0 ). The equations required to specify the state for all t t 0, given the initial state and the input u(t), t t 0, are called state equations. The state space X of the system is the set of all possible values of the state.
16 System Modeling, JanFeb 2005, Kista Introduction 15 The State Space Continuousstate models: The state space X is a continuum, e.g. X = R or X = R n Discretestate models: The state space is a discrete set, e.g. X = N or X = {0, 1} or X = { blue, red, green }.
17 System Modeling, JanFeb 2005, Kista Introduction 16 A State Space Model for Continuous Time, Continuous State Systems State equations: Initial state: x(t) = g( x(t), u(t), t) Output equations: x(0) = x 0 y(t) = f( x(t), u(t), t)
18 System Modeling, JanFeb 2005, Kista Introduction 17 State equations: A State Space Model for Discrete Time Systems Initial state: x(t + 1) = g( x(t), u(t), t) Output equations: x(0) = x 0 y(t) = f( x(t), u(t), t)
19 System Modeling, JanFeb 2005, Kista Introduction 18 A State Space Model for TimeInvariant, Discrete Time Systems State equations: Initial state: x(t + 1) = g( x(t), u(t)) Output equations: x(0) = x 0 y(t) = f( x(t), u(t))
20 System Modeling, JanFeb 2005, Kista Introduction 19 Linear and Nonlinear Systems Definition: A function f : A A is linear if and only if f(a 1 x 1 + a 2 x 2 ) = a 1 f(x 1 ) + a 2 f(x 2 ) for all a 1, a 2, x 1, x 2 A. A function f : A n A n is linear if and only if f(a 1 x 1 +a 2 x 2 ) = a 1f( x1 )+a 2f( x2 ) for all a 1, a 2 A, x 1, x 2 A n, where A n is the set of vectors of length n with elements of A. A system with state function g and output function f is linear if and only if both functions f and g are linear.
21 System Modeling, JanFeb 2005, Kista Introduction 20 Matrix Equations for Discrete, Linear Systems x(t + 1) = A(t) x(t) + B(t) u(t) y(t) = C(t) x(t) + D(t) u(t) where A(t) n n matrix, B(t) n p matrix, C(t) m n matrix, D(t) m p matrix, n number of state variables, m number of output variables, p number of input variables.
22 System Modeling, JanFeb 2005, Kista Introduction 21 Matrix Equations for Discrete, Linear, Timeinvariant Systems x(t + 1) = A x(t) + B u(t) y(t) = C x(t) + D u(t) with constant matrices A, B, C, and D.
23 System Modeling, JanFeb 2005, Kista Introduction 22 Deterministic, Stochastic and Nondeterministic Systems Definition: A system model is deterministic if the output function f and the state function g are functions in the sense that they evaluate a given argument always and unambiguously to the same result. A system model is stochastic if at least one of their output variables is a random variable. A system model is nondeterministic if a given input may result in different outputs.
24 System Modeling, JanFeb 2005, Kista Introduction 23 Events Events are associated with a time instance and have no duration. Examples: Arrival of a message; Change of a signal value; Change of a state; A counter exceeding a given threshold value; An elapsed time period; etc.
25 System Modeling, JanFeb 2005, Kista Introduction 24 Timedriven and Eventdriven In timedriven systems the advance of time causes the system to become active. In eventdriven systems the occurrence of an event causes the system to become active.
26 System Modeling, JanFeb 2005, Kista Introduction 25 System Classification Summary Systems Static Dynamic Time varying Time invariant Linear Non linear Systems under consideration Continuous state Discrete state Continuous time Discrete time Event driven Time driven Deterministic Stochastic Nondeterministic
27 System Modeling, JanFeb 2005, Kista Introduction 26 The Rugby MetaModel Abstraction in four domains Computation Communication Time Data
28 System Modeling, JanFeb 2005, Kista Introduction 27 Example of a Hierarchy
29 System Modeling, JanFeb 2005, Kista Introduction 28 Example of an Abstraction
30 System Modeling, JanFeb 2005, Kista Introduction 29 Ways to Handle Complexity Complexity Domains Hierarchy Abstraction Analytic aproach Horizontal approach Vertical approach
31 System Modeling, JanFeb 2005, Kista Introduction 30 Hierarchy, Abstraction, Domain Hierarchy: A hierarchy is a, possibly recursive, partitioning of a design model such, that the details of each part is hidden into a lower hierarchical level. Moving down the hierarchy displays information. Moving up the hierarchy hides information. Abstraction: An abstraction level defines the modeling concepts and their semantics for representing a system. The type of information available at different levels is different. A higher level ignores some irrelevant information of a lower level or encodes it using different concepts. Moving down an abstraction level adds information. Moving up an abstraction level removes information. Domain: A domain is an aspect of a model which can logically be analyzed independently from other aspects.
32 System Modeling, JanFeb 2005, Kista Introduction 31 Rugby Time Computation Idea Physical System High abstraction Communication Data Low abstraction Development time line
33 System Modeling, JanFeb 2005, Kista Introduction 32 Structure and Interface Constraints The Domains in Rugby Communication Inter Process Communication Topology Procedure Call Layout HW SW Relations and Constraints Computation System Function Concurrent Processes Algorithm Logic Block Transistor Instruction Set HW SW Data Data Type Constraints Symbol Number Continuous Value Logic Value HW Time Timing Constraints Causality ClockedTime Physical Time HW Processor Data Types SW Processor Cycle Time SW Idea Physical System Development timeline High Abstraction Low Abstraction
34 System Modeling, JanFeb 2005, Kista Introduction 33 The Computation Domain System Constraints Relations and System Function Concurrent Processes Algorithm Logic Block Set Transistor Instruction HW SW
35 System Modeling, JanFeb 2005, Kista Introduction 34 A MOS Transistor Model V DS > V GS V T (conducting state): I D = k n W W 2L (V GS V T ) 2 (1 + λv DS ) Gate Drain I D Source V DS < V GS V T (subthreshold state): I D = k n W W L ((V GS V T )V DS V 2 DS 2 ) where V T = V T 0 + γ( 2φ F + V SB 2φ F ) V DS... drainsource voltage V GS... gatesource voltage V T... threshold voltage... drainsource current I D
36 System Modeling, JanFeb 2005, Kista Introduction 35 A Transistor as Switch Gate Drain Source Gate Drain Source 0 0 undefined 0 1 undefined
37 System Modeling, JanFeb 2005, Kista Introduction 36 An AND Gate as Transistor Network Input 1 Input 2 Input 3 Input 4 1 R 0 Output Two problems with arbitrary transistor networks: Output is not defined when input is 0. Voltage drop between drain and source is relevant but not visible.
38 System Modeling, JanFeb 2005, Kista Introduction 37 An Inverter as Transistor Network Drain Input Output 2 Input Output Source (b) (c) (a)
39 System Modeling, JanFeb 2005, Kista Introduction 38 Gate Based Abstraction Level 1. The primitive elements are defined by simple models, i.e. small truth tables in this case. 2. The primitive elements can be implemented in a wide range of technologies. 3. The model holds even for arbitrarily large networks of primitive elements.
40 System Modeling, JanFeb 2005, Kista Introduction 39 Algorithms, Functions, Relations Relation [n 1, n 2,...n N ] n SORT i =, <, > n i+1 [n 1, n 2,...n N ] [n 1, n 2,...n N ] [n 1, n 2,...n N ] n i >= n i+1 Function [n 1, n 2,...n N ] n SORT i =, <, > n i+1 [n 1, n 2,...n N ] n i >= n i+1 Algorithm Bubble sort for i := 2 TO N do for j := N downto i do if input [j1] > input [j ] then begin tmp := input [ j 1 ]; input [ j  1] := input [ j ]; input [ j ] := tmp; end Linear sort Quick sort
41 System Modeling, JanFeb 2005, Kista Introduction 40 Sorting Defined as Relation sort (IntArray A) (IntArray B) Precondition: true Post condition: a A : a B b B : b A i, j Integer, b i, b j B : i < j b i b j
42 System Modeling, JanFeb 2005, Kista Introduction 41 Sorting Defined as Function sort ::[Integer] [Integer] sort [] = [] sort (x : xs) = (sort (selectlt x xs)) + + [x] + + (sort (selectge x xs))
43 System Modeling, JanFeb 2005, Kista Introduction 42 Sorting Defined as Algorithms Array sort s (iarray) { Array oarray = EArray; // initialized to the empty array int x = iarray[0]; oarray = sort s(selectlt (x,iarray)); append(orray,x); append(oarray,sort (selectge (x,iarray))); return (oarray); } a sequential algorithm Array sort p (iarray) { Array oarray,oarray2 = EArray; int x = iarray[0]; par{ oarray = sort p(selectlt (x,iarray)) oarray2 = sort p(selectge (x,iarray)) } append(orray,x); append(oarray,oarray2); return (oarray); } a parallel algorithm
44 System Modeling, JanFeb 2005, Kista Introduction 43 The Communication Domain Structure and Interface Constraints Inter Process Communication Topology Layout HW System Procedure Call SW
45 System Modeling, JanFeb 2005, Kista Introduction 44 Communication at the Gate and Layout Level b a c a b x NAND INV c y OR NAND y x
46 System Modeling, JanFeb 2005, Kista Introduction 45 Communication between Processes Communication Network A B
47 System Modeling, JanFeb 2005, Kista Introduction 46 The Data Domain Constraints Data Type Symbol Number Continuous Value Logic Value HW System Data Types Processor SW
48 System Modeling, JanFeb 2005, Kista Introduction 47 The Time Domain Timing Constraints Causality ClockedTime Physical Time HW System Processor Cycle Time SW
49 System Modeling, JanFeb 2005, Kista Introduction 48 Notation for Abstraction Levels: Computation Relations and Constraints RelationConstraints RC System Functions SystemFunctions SF Concurrent Processes, Algorithms Algorithm Alg Logic Block LogicBlock LB Transistor Transistor Tran Instruction Set InstructionSet Inst
50 System Modeling, JanFeb 2005, Kista Introduction 49 Notation for Abstraction Levels: Communication Structural and Interface Constraints InterfaceConstraints IC Inter Process Communication InterProcessComm IPC Topology Topology Top Layout Layout Lay Procedure Call ProcCall PC
51 System Modeling, JanFeb 2005, Kista Introduction 50 Notation for Abstraction Levels: Data Data Type Constraints DataTypeConstraints DTC Symbol Symbol Sym Number Number Num Logic Value LogicValue LV Continuous Value ContValue CV Processor Data Types ProcessorDataTypes PDT
52 System Modeling, JanFeb 2005, Kista Introduction 51 Notation for Abstraction Levels: Time Timing Constraints TimingConstraints TC Causality Causality Caus Clocked Time ClockedTime CT Physical Time PhysicalTime PhyT Processor Cycle Time ProcessorCycleTime PCT
53 System Modeling, JanFeb 2005, Kista Introduction 52 Abstraction Levels in Design Phases RC SF Alg LB IC IPC Top DTC Sym Num LV TC Caus CT PhyT Requirements Definition Specification Design Implementation Development Timeline Tran Lay CV Computation Communication Data Time
54 System Modeling, JanFeb 2005, Kista Introduction 53 Design Activities in Terms of Abstraction Levels RC IC DTC TC System Partitioning Technology mapping SF Alg LB Tran Interface Synthesis Place&Route IPC Top Lay State encoding Technology mapping Sym Num LV CV Scheduling Retiming Caus CT PhyT Computation Communication Data Time
55 System Modeling, JanFeb 2005, Kista Introduction 54 Analysis Activities in Terms of Abstraction Levels Feasibility analysis IC RC DTC TC IPC Logic simulation, Timing analysis Top SF Alg LB Sym Num LV Caus Performance estimation of algorithms CT PhyT Lay Area estimation of algorithms Communication Tran Computation CV Data Time
56 System Modeling, JanFeb 2005, Kista Introduction 55 The Network Terminal Case Study Network Terminal (NT) 0 1 Backbone network
57 System Modeling, JanFeb 2005, Kista Introduction 56 The Network Terminal Case Study CPN Interface NT Core Ethernet Control and Access Network Distribution Network Interface Block Management ATM Switch Telephone Cable TV
58 System Modeling, JanFeb 2005, Kista Introduction 57 The NT Design Flow Requirements SDL Model C Model VHDL Model Assembler Netlist
59 System Modeling, JanFeb 2005, Kista Introduction 58 Models in the NT Design Models Abstraction Levels Computation Communication Data Time Requirements RC IC DTC TC System (SDL) Alg IPC Sym Caus HW VHDL Alg Top Sym,LV CT Netlist LB Top LV PhyT SW C ALg PC Sym CT Assembler Inst PC PDT PCT
60 System Modeling, JanFeb 2005, Kista Introduction 59 The Network Terminal Case Study Time Idea Requirements High abstraction Specification (SDL) Computation Communication Data Design models (VHDL and C) Implementation (Assembler, Netlist) Low abstraction Physical System Development time line
61 System Modeling, JanFeb 2005, Kista Introduction 60 Transformations in the NT Design Requirements Algorithmic: Computation Time Algorithmic: Computation Communication Data Time C Model Assembler SDL Model Algorithmic transformation: none Algorithmic: Computation VHDL Model Netlist Algorithmic: Computation Communication Data Time
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