Technology, Devices and Circuits for Energy-Efficient Computing
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1 Technology, Devices and Circuits for Energy-Efficient Computing Professor Per Larsson-Edefors Computer Science and Engineering Chalmers University of Technology Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 1
2 Motivation Physical implementation impacts power dissipation. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 2
3 Field-Effect Transistor Basics The MOSFET; the work horse of all digital systems. Voltage is applied on gate. Electric field regulates material properties beneath gate. Threshold voltage (V TH ) is the gate voltage required to create a conducting channel. Channel Source: USC Body electrode Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 3
4 Switching Power Dissipation in CMOS, 1 g d s Q C CMOS inverter. Input transition 1 0 output node 0 1, requiring charge Q = C V DD from the power supply. Later, input 0 1 output node falls, draining the charge to the ground. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 4
5 Switching Power Dissipation in CMOS, 2 P sw = f C V DD 2 After one full transition, the energy of the charge is converted into heat: P sw = E/T = (Q V)/T = (CV V) f. To reduce switching power 1. reduce supply voltage (V DD ). 2. reduce clock frequency (f). 3. reduce signal activity ( ). 4. reduce nodal capacitance (C). Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 5
6 Energy, Speed, and Power Backing off speed (using weaker circuits) saves power, but energy/operation is almost the same. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 6
7 Scaling Supply Voltage for Reduced P sw So V DD is decreased to save switching power. Since performance deteriorates rapidly as V DD approaches V TH, V TH has to be decreased as well. Source: SSD 13 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 7
8 Voltage Scaling Issues Source: H. Iwai, Technology Scaling and Roadmap, IEDM'08/Short Course Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 8
9 CMOS Stability Reduces with Scaling Classic advantage of CMOS: High I ON /I OFF ensures stable, digital operation. But because of scaling, subthreshold leakage ( e -V TH) increases I OFF increases. Degrading I ON /I OFF ratio limits how far V DD can be scaled. This is a critical issue in SRAMs. 0 1 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 9
10 Subthreshold/Nearthreshold Computing Source: NTC 10 Minimal energy/operation makes near-threshold (NVT) operation interesting; however performance is very poor. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 10
11 Delay vs VDD Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 11
12 Energy/operation vs VDD Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 12
13 MOSFET Subthreshold Swing Source: BTBTFET 10 S (= SS above) >= = 59.8 mv/decade. m = 1+ C depletion-layer /C gate-oxide Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 13
14 Subthreshold Operation S >= 60 mv/decade for MOSFETs. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 14
15 Post-CMOS Tunnel-FETs? Source: BTBTFET 10 A lower subthreshold swing gives acceptable I ON /I OFF ratios at low supply voltages. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 15
16 TFET vs CMOS Source: OBCD'13 TFETs (e.g. HetJFET) are promising but CMOS is not doing that bad The challenge is to make TFETs that can both have subthreshold swings << 60mV/decade high I ON currents Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 16
17 Conventional Low-Power Techniques Body biasing Multi-V TH Multi-V DD DVFS Clock gating Power gating Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 17
18 Low-Power Technique 1: Body Biasing In e -V TH, V TH depends on MOSFET terminal voltages. In an NMOSFET, V TH decreases with an increasing body voltage (V B ). 0 1 V B Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 18
19 Body Bias for Perf. and Power Binning Reverse body biasing (RBB) V B < 0 V (NMOSFET) V TH increases. leakage decreases. Forward body biasing (FBB) V B > 0 V (NMOSFET) V TH decreases. higher speed. Of limited use in advanced bulk CMOS. Incompatible with FinFET technology. Source: ABB 02 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 19
20 Fully Depleted-Silicon on Insulator (FD-SOI) 1-V V B change 85-mV V TH change. FD-SOI for low-power rather than high-speed. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 20
21 Bulk and SOI FinFETs Source: IBM14nm Source: Intel14nm IBM SOI-based FinFETs Intel Bulk FinFETs Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 21
22 Delay Distribution of Logic Logic paths exhibit different delays. Critical paths must satisfy clock rate constraint implementation must ensure gates are fast enough. But what about the fast paths can their intrinsic speed be converted to power reductions? Source: LPDE 09/Ch 4 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 22
23 Low-Power Technique 2: Multi-V T Source: LPDE 09/Ch 4 Assign fast paths to slow transistors use transistors with high V TH leakage is reduced. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 23
24 Match V DD to Performance Need Source: LPDE 09/Ch 4 First order delay 1/V DD and P V DD2 : Reduce V DD for circuits that are not timing critical. How many different V DD levels should be used? Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 24
25 Low-Power Technique 3: Multi-V DD Dual- V DD ALU example from LPDE 09/Ch 4 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 25
26 Low-Power Technique 4: DVFS Slack can be used for power reductions: Dynamic Voltage and Frequency Scaling. Read more in CATPE 08/Ch 3 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 26
27 Circuit Adaptation for DVFS Aggressive V DD reduction causes timing violations. Implement a feedback system that regulates speed, in the process also handling variations. Read more in CATPE 08/Ch 3.5 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 27
28 Example on Variations Clock arrival times are hard to synchronize. Source: POWER 11 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 28
29 Detection of Timing Failures High clock rates or extremely compute-intensive code can expose timing issues. Source: ARM 11 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 29
30 Low-Power Technique 5: Clock Gating Source: LPDE 09/Ch 8 Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 30
31 Recap: Low-Power Techniques Body biasing Multi-V TH Multi-V DD DVFS Clock gating Power gating Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 31
32 Low-Power Technique 6: Power Gating Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 32
33 Power Gating of Execution Unit Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 33
34 Power Gating after Place&Route Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 34
35 Power Gating Impacts Area Significantly Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 35
36 Identify Multiply Activity Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 36
37 Limited Utilization Allows for Savings EEMBC Autocorrelation EEMBC FFT Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 37
38 Low-Power Options Pros and Cons Source: Cadence Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 38
39 Power Reductions in Design Flow Early design decisions yield higher power reductions than late decisions. Important for system architects to know which low-power techniques can be used. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 39
40 Missed Opportunities? Low-power techniques clearly exist. But how do we make use of them in complex systems? Designer s competence + EDA tools. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 40
41 Industry View on Low-Power Techniques Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 41
42 Conclusion Choice of technology, devices and circuits is vital to power and energy efficiency. Different reasons for power dissipation and, thus, different techniques to reduce power. To reduce power dissipation, you need to stay well informed: Power and energy analysis is complex since it depends on use case scenarios. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 42
43 References, 1 ABB 02: Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage, J. Tschanz et al., IEEE JSSC, Nov ARM 11: A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation, D. Bull et al., IEEE JSSC, BTBTFET 10: Band-to-Band Tunneling Field Effect Transistor for Low Power Logic and Memory Applications, S. A. Mookerjea, PhD Thesis, Penn State Univ, CATPE 08: Computer Architecture Techniques for Power-Efficiency, S. Kaxiras and M. Martonosi, Morgan & Claypool, Intel14nm: A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a µm2 SRAM cell size, S. Natarajan et al., IEEE Int. Electron Devices Meeting (IEDM), Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 43
44 References, 2 IBM14nm: High Performance 14nm SOI FinFET CMOS Technology with μm2 embedded DRAM and 15 Levels of Cu Metallization, C.-H. Lin et al., IEDM LPDE 09: Low Power Design Essentials, J. Rabaey, Springer, NTC 10: Near-Threshold Computing: Reclaiming Moore s Law Through Energy Efficient Integrated Circuits, R. G. Dreslinski, et al., Proc. of IEEE, Feb OBCD'13: Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking, D. E. Nikonov, Proc. of IEEE, Dec POWER 11: POWER7, a Highly Parallel, Scalable Multi-Core High End Server Processor, D. F. Wendel et al., IEEE JSSC, SSD 13: Steep-Slope Devices: From Dark to Dim Silicon, K. Swaminathan et al., IEEE Micro, And many local Chalmers papers. Technology, Devices and Circuits for Energy-Efficient Computing, 2016 Page 44
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