4. Wafer Manufacturing, Epitaxy, and Substrate Engineering

Transcription

1 4. Wafer Manufacturing, Epitaxy, and Substrate Engineering Single crystal in nature: quartz (SiO 2 ), ruby (Al 2 O 3 with the presence of Cr), sapphire (Al 2 O 3 with the presence of with mpurities other than Cr), and diamond (carbon). 4.2 Why silicon? About 26% of earth s crust is silicon, second only to oxygen. The cost of a single-crystal becomes much lower than any other single-crystal semiconductor material. A layer of SiO 2 can easily grow on its surface in a thermal oxidation process, whereas GeO 2 is difficult to form, unstable (>800 C), and water soluble. Silicon has a larger bandgap, capable tolerate higher operating temperatures and wider doping ranges. It also has a higher breakdown voltage than germanium. Silicon dioxide as a doping mask: Diffusion rate of dopants in SiO2 << that in Si For metal-insulators emiconductor (MIS) transistors, the SiO 2 Si interface has superior electrical characteristics for MOS 1

2 4.3 Crystal Structures and Defects Crystal orientation The most commonly used silicon crystal orientations are <100> and <111> Crystal defects 2

3 4.4 Sand to Wafer From sand (SiO 2 ) to Si wafer MGS (metallurgical-grade silicon98-99%) TCS (trichlorosilane, %, 9N) : High-purity TCS is one of the most commonly used silicon precursors for Sideposition. It is widely applied to amorphous silicon, polysilicon, and epitaxial silicon depositions. EGS (electronic-grade silicon): high-purity polysilicon. single-crystal silicon ingots wafers. 3

4 4.4 Sand to Wafer Both the CZ (Czochralski) and floating zone methods are used for wafer manufacturing. CZ method: More common, cheaper and producing larger-sized wafers, impurities of oxygen and carbon from crucible. Floating zone: higher purity. 4

5 4.4 Sand to Wafer 切除 側邊研磨 (150 mm or smaller) or notch (200 mm or larger) 5

6 4.4 Sand to Wafer 機械磨邊 Double side lapping: under pressure + glycerin slurry with fine alumina (Al 2 O 3 ) particulate suspended in it. A wafer with a surface flatness within 2 μm and removes about 50 μmm of silicon from both sides of a 200-mm wafer. Wet etch: HNO 3 (79 wt%, Si oxidized to SiO 2 ) + HF (49 wt%, remove SiO 2 ) + pure CH 3 COOH (control etching rate), 4: 1: 3. CMP: A pressed rotating wafer + a rotating polishing pad + slurry and water in between. Slurry - colloidal fine silica (SiO2, d~ 100 Å) suspended in NaOH(aq). Post CMP clean: SC-1, SC-2, Piranha clean. 6

7 4.5 Epitaxial Silicon Deposition The epitaxial silicon layer is needed for bipolar devices and improves performance for CMOS and DRAM. The IC industry uses hightemperature CVD processes to grow epitaxial silicon layers. 7

8 4.5 Epitaxial Silicon Deposition At lower temperatures (550 to 650 C) in a low-pressure reactor, a silane-based reaction can be used to deposit polycrystalline silicon on a singlecrystal silicon wafer surface. The first regime is called the surfacereaction-limited regime, and the second is called the mass-transportlimited regime. 8

9 4.5 Epitaxial Silicon Deposition Batch reactors: Wafers loaded on the susceptor purged with hydrogen temperature raised to 1150 to 1200 C HCl (~3 min)to clean the chamber surface and etch the wafer surface to remove native oxide, particles, and surface defects. minimize the mobile ions, especially sodium contamination. Chamber to the required process temperature. silicon and dopant precursor gases flow into the chamber to grow the epitaxial silicon layer at a growth rate of 0.2 to 4.0 μm/min. Hydrogen again flows into the chamber to purge the processing gases. When the temperature drops low enough, nitrogen purges the chamber to an ambient temperature, and the chamber is ready to open, unload, and reload. WPH~10 to 28. Q: Why H 2 as the main purge gas? Ans: At >1000 C, nitrogen can react with silicon to form silicon nitride. For a single-wafer system, thermal capacity is small. An array of heating lamps ramps up very quickly. After epitaxial-layer deposition, transfer red to a cool-down chamber. Defect types: 9

10 4.5 Epitaxial Silicon Deposition Future trends of epitaxy Low temperature epitaxy (LTE): - Reduced-pressure epitaxial growth at 40 to 100 torr and ~1000 C, at 0.01 to 0.02 torr and 750 to 800 C. - Ultrahigh-vacuum CVD (UHV-CVD) epitaxial growth processes at 10 6 to 10 9 torr with low temperatures of 550 to 650 C. Applications: silicon-germanium (SiGe) epitaxial layer on a silicon substrate with SiH 4 and GeH 4. Why? Collisions between molecules in gas phase reactions are unlikely. No hydrodynamic boundary layer by molecular flow. A growth rate is determined by surface decomposition of the reactant molecules Selective epitaxy The selective epitaxial growth (SEG) process has been widely used to deposit SiGe in the pmos S/D area to help create uniaxial compressive strain in the pmos channel, increasing hole mobility and improving pmos drive current and speed. 10

11 4. Wafer Manufacturing, Epitaxy, and Substrate Engineering 4.6 Substrate Engineering Silicon-on-insulator wafer Separation by implantation of oxygen (SIMOX) 11

12 4. Wafer Manufacturing, Epitaxy, and Substrate Engineering 4.6 Substrate Engineering Hybrid orientation technology (HOT) (1) By using a <110> orientation wafer as wafer A in Fig and a <100> orientation wafer as wafer B, a hybrid orientation SOI wafer can be made. (2) In Fig. 4.28: Hybrid <110> and <100> on the wafer surface. <100> for n-mos <110> for p-mos 12

13 4. Wafer Manufacturing, Epitaxy, and Substrate Engineering 4.6 Substrate Engineering Strained silicon wafer Strained silicon-on-insulator wafer Strained silicon: Stretched or compressed beyond normally interatomic distance of Si. Carrier mobility in strained silicon can be significantly higher than that in strain-free silicon. SSOI: Strained silicon on insulator. By using existing process technologies (Chap ), creating strained silicon locally on a normal silicon wafer. not necessary to strain the entire surface of a silicon wafer. pmos prefers compressive strain to enhance hole mobility nmos needs tensile strain to enhance electron mobility A strained silicon wafer cannot satisfy both needs. 13

14 4.6 Substrate Engineering Strained silicon in integrated circuit manufacturing Dual stress liners: - Compressive stress liners on pmos, using selective epitaxial SiGe. - Tensile stress SiC liners on nmos 14