High-temperature CVD silicon films for crystalline silicon thin-film solar cells

Transcription

1 High-temperature CVD silicon films for crystalline silicon thin-film solar cells Dissertation zur Erlangung des akademischen Grades des Doktors der Naturwissenschaften (Dr. rer. nat.) an der Universität Konstanz Fakultät für Physik vorgelegt von Sandra Bau Fraunhofer Institut für Solare Energiesysteme Freiburg 2003

2 Referenten: Priv. Doz. Dr. Gerhard Willeke Prof. Dr. Wolfram Wettling

3 Contents 1 Introduction 1 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells Principle of CSiTF solar cells General CSiTF solar cell components Thin Film Concepts Low-temperature approach High-temperature approach Transfer techniques Chemical vapor deposition (CVD) of silicon Silicon deposition techniques Liquid Phase Epitaxy (LPE) Physical Vapor Deposition (PVD) Chemical Vapor Deposition (CVD) Overview on deposition techniques and applications Deposition principle of silicon by thermal CVD Transport Thermal equilibrium conditions Reaction kinetics Chemical yield Reactor design for APCVD APCVD at Fraunhofer ISE Reactor design RTCVD RTCVD Continuous CVD (ConCVD) Summary Process Optimization for RTCVD Metrology Thickness measurement Doping control Impurity concentration measurements by SIMS Defects Lifetime measurement by MW-PCD i

4 4.2 Epitaxial deposition Pre-epitaxial sample cleaning Thickness uniformity Doping of epilayers Crystal quality Lifetime measurements Chemical analysis Surface morphology of multicrystalline layers Silicon deposition on foreign substrates Thickness uniformity Doping of seeding layers Layer growth in RTCVD Summary Doping of epitaxial silicon layers Dopant incorporation Doping profiles of epitaxial layers Experimental carrier concentration profiles Boron diffusion and evaporation Background doping and memory effect Doping profile of intrinsic epilayers Standard epitaxy Deposition with pre-epitaxial diffusion High-low deposition Effect of doping profile on solar cell performance Improved gas system design Summary Epitaxial thin-film solar cells Solar cell concept Silicon substrate materials Efficiency Epitaxial deposition systems Efficiency table for epitaxial thin-film solar cells Solar cells on Cz-Si substrates Solar cell processing RTCVD-process A vs. B Epilayer quality Comparison of solar cell technologies Overview on solar cell efficiencies Characterization by lock-in thermography Summary ii

5 6.2.8 Solar cell simulation Solar cells on mc-silicon substrates Solar cells on reclaimed silicon wafers Front surface texturing for epitaxial cells Innovative solar cell technology by CVD Emitter epitaxy Boron BSF epitaxy and diffusion In-situ HCl texturing Summary Silicon thin-film solar cells on insulating substrates Solar Cell principle and technology Layer system Cell technology Silicon thin-film solar cells on ceramic substrates Material and solar cell preparation Silicon thin-films on silicon-infiltrated silicon carbide ceramics (SiSiC) Silicon thin-films on hot-pressed silicon nitride ceramics Silicon thin-films on tape cast silicon nitride ceramics Silicon thin-films on SiAlON ceramics Summary Summary 145 Deutsche Zusammenfassung 149 Appendix A Abbreviations 153 Appendix B Solar cell fundamentals 155 Bibliography 159 Publications 171 Acknowledgements 173

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7 1 Introduction The development of renewable energies is motivated by the wish to avoid the problems associated to nuclear and fossil energy production and to use environment-friendly energy sources instead. During the last decade the photovoltaic (PV) market has experienced a steady growth of 15-25% with the growth rate even exceeding 40% in 2000 [1]. In the near future a further increase in growth rate is expected. Despite this rising trend, energy production by photovoltaic sources only plays a minor role with respect to the world s energy production. At present, PV electric energy is still more costly than grid electricity and government subsidies programs are running to support the application of PV systems. Today s PV module market is dominated by crystalline silicon solar cells. In 2001, about 91% of the PV market share were held by crystalline silicon, the major part being provided by polycrystalline (48%) and single-crystal (35%) material (Figure 1.1). Silicon solar cell manufacturing benefits from a mature technology and expertise available from microelectronics, non-toxicity, long-term stability and large material abundance of silicon. Thin-film technologies like amorphous silicon (a-si:h), CIS (CuInGaSe 2 ) and CdTe make up for only a small fraction of the world s module market. While the efficiency of a-si:h modules still ranges on a comparatively low level of 8%, and CIS solar cells have to deal with a possible indium bottleneck, CdTe is the least attractive material due to the high toxicity of Cd and Te. The latter two technologies have just about started pilot-line production. a-si on Cz Slice 4.63% Ribbon Si 3.5% Si Film 0.26% Amorphous Si 8.3% CIS 0.18% Cadmium Telluride 0.42% Single Crystal Si 35.17% Polycrystal Si 47.54% Figure 1.1: Market shares of photovoltaic materials (after [2]). About 40% of the silicon module cost are made up by the silicon wafer [3]. With increasing growth of the photovoltaic market, the demand for crystalline silicon material will rise. Currently, the PV industry obtains silicon wafers and raw material from microelectronic production: off spec, pot-scrap, tops and tails from electronic grade silicon production are used as silicon sources for solar cell manufacturing [4]. The price for a silicon wafer and with that the module price is therefore highly dependent on the microelectronic market. With growing PV industry the need for crystalline silicon 1

8 2 1 Introduction wafers will permanently rise, while in microelectronics the trend goes to smaller devices and higher device density per wafer i.e. lower material consumption and production. The two counteracting trends led to an imminent silicon feedstock bottleneck for PV applications. Today s research activities seek to avoid or diminish this shortage by the development of alternative silicon solar cell concepts with reduced silicon consumption and by the establishment of an independent solar grade silicon production [5]. In the long term, thin-film cells (silicon or other materials) are assumed to become the market dominating technology. The concept of crystalline silicon thin-film (CSiTF) solar cells can substantially reduce silicon material consumption and has the potential to reach high efficiencies comparable to wafer silicon solar cells. During the past decade a lot of research has been done on this subject and a large variety of silicon thin-film solar cell concepts have been investigated. At present, none of the approaches has made a final breakthrough to industrial production and the neck-and-neck race continues to push research activities further on. This work deals with the deposition of silicon films for CSiTF solar cells and the realization of this cell concept by different approaches. The following chapter explains the basic components of a crystalline silicon thin-film solar cell and gives an overview on current approaches. In the third chapter, silicon deposition techniques are reviewed and the potential of atmospheric pressure chemical vapor deposition (APCVD) for an application in CSiTF solar cell technology is motivated. The silicon deposition process by chemical vapor deposition is theoretically explained and an example for a silicon growth model is given. Subsequently the silicon deposition and reactor design pursued at Fraunhofer ISE is presented. The APCVD reactor concept is adapted to the needs of photovoltaic industry an therefore differs from commercial reactor configurations. Technical details are discussed and key features of the reactor design are explained. The characterization and optimization of silicon epitaxial layers (epilayers) and silicon layers on foreign substrates (seeding layers) by APCVD is presented in chapter four. Silicon films grown under different process conditions are analyzed and standard processes are defined, which allow for a deposition of silicon layers with well defined properties. The controlled growth of silicon films is a prerequisite for a successful preparation of any device based on these layers and the results obtained during the optimization process are therefore of great importance for the entire work. The detailed characterization of carrier concentration profiles in silicon epilayers by Spreading Resistance Profiling is subject of chapter five. Important insight on the effect of the gas system on carrier concentration profiles and on the mechanisms of boron incorporation during silicon deposition can be obtained from this analysis. Chapter six deals with the preparation of epilayers on different electrically inactive silicon substrates for a preparation of epitaxial silicon thin-film solar cells. The application of industrial type solar cell processing techniques on epitaxial material is a main topic of this work and an extensive investigation of possible interactions between epilayers and different solar cell process steps is carried out. The use of multicrystalline and potential low-cost reclaimed silicon wafers as substrates is studied. In the last chapter, silicon thin-film solar cells on non-conductive ceramic substrates are investigated. Silicon films are prepared on four different ceramic substrates by silicon layer deposition, recrystallization and epitaxy of the base layer. Sample structure and solar cell performance are characterized in detail and the suitability of the applied ceramic substrates is evaluated.

9 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells Reduction in final module cost is one of the basic motivations in silicon solar cell research today. Main focus is put on a reduction in electronic grade silicon usage and solar cell concepts consuming less silicon material and ways to bypass the silicon feedstock bottleneck are currently investigated. The concept of crystalline silicon thin-film solar cells tackles this problem by using an active device region which is reduced to a thin layer, only about one tenth of conventional wafer cells. The fundamental principles and different approaches for CSiTF solar cells are reviewed in this chapter. 2.1 Principle of CSiTF solar cells General Cost-saving is the key word associated to most solar cell research subjects today. Considering the cost breakdown for a commercial silicon PV module, the silicon wafer makes up for 42% of the final module cost, while the remaining 58% are shared by module fabrication and solar cell technology [3]. With increasing growth of silicon module production the consumption of electronic grade silicon for PV applications rises and silicon feedstock is assumed to get short in the future, leading to an increase in material cost. The largest cost-saving potential in silicon module production can be expected from the silicon wafer. Reducing silicon feedstock cost and lowering silicon consumption are two ways to reduce the price for silicon solar cell material. The latter solution is addressed in the following. Conventional silicon solar cells are prepared on silicon wafers of µm thickness. The technology used for wafering and the need for mechanical stability of the device determine the wafer thickness. With respect to solar cell performance thinner base layers have the potential to yield similar or even higher efficiencies compared to conventional thick wafer cells and therefore many research groups follow a thin silicon film approach to reduce material consumption. - Thin wafers Wire sawing of silicon ingots is state-of-the-art technology for the production of silicon wafers resulting in wafer thickness of µm with a kerf loss in the range of 200 µm. From a technical point of view a reduction of kerf loss is difficult to realize, due to an increased danger of wire breakage with decreasing saw wire thickness. Reducing the wafer thickness and therefore increasing wafer output is more feasible and can substantially lower material cost [6], [5] without suffering from efficiency losses. While the production of thin wafers (~100 µm thickness) is already technically feasible, solar cell processing of these wafers is still a problem due to the increased fragility of the material. At present, research activities in this area deal with the development of new wafering technologies and the development of solar cell processes adapted to the properties and needs of thin wafers. 3

10 4 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells - Silicon ribbons Silicon ribbon technologies bypass the necessity for ingot production and the associated loss in silicon material. The edge-defined film-fed growth (EFG) by ASE is the most mature ribbon technology. Following this approach, silicon sheets with a thickness of µm are directly pulled from the melt, laser cut and used as silicon wafer material. The String Ribbon technique by Evergreen Solar, the Dendritic Web by Ebara, RGS (ribbon growth on substrate) by ECN (Netherlands Energy Research foundation) and SSP (silicon sheets from powder) by Fraunhofer ISE constitute other important silicon ribbon techniques. Higher throughput and further decrease in film thickness are two major issues in silicon ribbon development to become industrially relevant technologies. An overview on this issue can be found in [7]. - Silicon thin-film solar cells The concept of silicon thin-film solar cells is based on the deposition of a thin (<50 µm) active silicon layer on a low-cost substrate. Within this approach the manufacturing of silicon ingots and wafering is avoided and material loss is mainly determined by the chemical yield of the deposition process. Moreover, silicon deposition from a gaseous source is used in most approaches with the silicon-containing source gas being an early element in the chain of silicon ingot production. The benefit from using a crystalline silicon thin-film concept compared to conventional wafer technology is the potential to reach high efficiencies at low material consumption. A detailed overview on crystalline silicon thin-film concepts is given in [8] and [9]. The cost per MWp photovoltaic electric power production is determined by module manufacturing cost, module efficiency and up-time. Therefore the choice of the solar cell concept to be followed is actually a trade-off between the two first aspects CSiTF solar cell components The working principle of a solar cell is extensively discussed in various textbooks and shall not be described here [10], [11] 1. Instead, the essential features of a CSiTF solar cell will be explained to enable an understanding of the device structure. Efficiency potential Reducing the thickness of a solar cell results in an increase in open-circuit voltage, if the short-circuit current can be maintained and surface recombination velocities are sufficiently low [12]. So, if efficient light trapping and surface passivation schemes can be provided, a solar cell with reduced thickness can even yield higher efficiencies compared to a corresponding thick wafer cell, assuming equal bulk diffusion lengths. This holds especially for low quality material featuring low minority carrier diffusion lengths. The potential of crystalline silicon thin-film solar cells and similarly thin crystalline silicon solar cells is based on these interrelations. An indicator which is often used to qualitatively estimate the potential of a solar cell is the ratio of cell thickness W to bulk diffusion length L n. Assuming zero surface recombination velocities and active base thickness substantially smaller than bulk diffusion length, the saturation current density is 1 A short introduction to solar cell device physics is given in the appendix.

11 2.2 Thin Film Concepts 5 proportional to the ratio W/L n i.e. the lower the base thickness at constant diffusion length, the lower the saturation current [12]. For low quality material, a reduction in base layer thickness is therefore of advantage. As a rule of thumb the effective minority carrier diffusion length in the base should exceed 2-3 times the layer thickness to achieve reasonable efficiencies for CSiTF solar cells. In the appendix, the correlation between saturation current, open-circuit voltage and the ratio W/L n is derived. Light trapping Silicon is an indirect semiconductor and a wafer thickness exceeding 140 µm is needed to absorb 90% of the incident photons of the solar spectrum (AM1.5) 2. Reducing the active base thickness to 20 µm a fraction of about 75% of the incident photons can be used for photocurrent generation [13]. The photon absorption capacity in a thin film can be increased by increasing the optical path length in the layer. Features leading to such an enhancement are commonly referred to as light trapping schemes. In silicon thin-film solar cells an efficient light trapping is mandatory to achieve high photocurrents despite the reduced absorber thickness. Surface texturing combined with a diffuse back side reflector effectively confines the incident light to the active device region. Apart from increasing the optical path length, the surface texturing also reduces reflection. Similarly, antireflection coatings deposited on the surface of the solar cell decrease the fraction of reflected light which is coupled into the bulk of the device instead. Surface and bulk passivation With decreasing device thickness surface recombination losses gain in importance and surface passivation schemes are indispensable. While the front surface can be well passivated by oxide or nitride layers, the rear surface of the active base region is given by the highly recombinative substrate surface for thin-film solar cells. Minority carriers reaching this surface quickly recombine and are lost for photocurrent generation. The implementation of a back surface field (BSF), a highly doped region at the back of the base, confines the minority carriers to the lower doped base region, thereby reducing the rear surface recombination losses. Recombination on grain boundaries dominates minority carrier lifetime in polycrystalline silicon thinfilm solar cells. Passivation of grain boundaries e.g. by hydrogen is often used to reduce recombination and increase bulk minority carrier lifetime. 2.2 Thin Film Concepts Traditionally, the solar cell concepts for crystalline silicon thin-film cells are divided into the so-called high-temperature and low-temperature approach, according to the maximum temperature the device can tolerate during processing. The threshold temperature is usually determined by the temperature stability of the substrate to be used. Within this classification the transfer (or lift-off) techniques take an exceptional position. Using this approach, epitaxial silicon films are grown at high or medium temperatures on ideal silicon wafers and subsequently transferred to low-cost, mechanically supporting substrates. So, with respect to the host substrate used for silicon deposition, this technique 2 AM1.5: Air Mass 1.5, standard solar spectrum used for terrestrial solar cell calibration. The sunlight passes an air mass which is by factor 1.5 larger compared to vertical incidence.

12 6 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells belongs to the high-temperature approach although the final supporting substrate is in general a lowtemperature material. In the following, the transfer techniques are discussed in a separate section. Common to all approaches is the need for a suitable high-rate silicon deposition tool to satisfy the need for high throughput imposed by industrial production Low-temperature approach Within the low-temperature approach, glass is the most prominent and most attractive substrate material. Borosilicate glasses and soda lime glasses are mechanically stable up to 650 C and 550 C respectively, and can be produced on a large scale at comparatively low cost. In addition, plastic films and steel have been investigated as potential low-cost substrates. Silicon deposition and solar cell processing have to be adjusted to the temperature limit imposed by these substrate materials. PECVD, IAD, and HWCVD 3 are widely used for the deposition of silicon layers at low temperatures in silicon thin-film solar cell R&D. These techniques are characterized by growth rates in the range of several ten nm/min and the deposited silicon films feature a crystal structure from microcrystalline 4 to amorphous. The latter characteristic represents a major drawback of the low-temperature approach, since the minority carrier lifetime in these materials is limited by recombination at grain boundaries. The application of recrystallization steps allows an enlargement of the grain size and therefore an increase in bulk diffusion length. However, due to the temperature restriction, the recrystallization process is confined to few low-temperature techniques e.g. solid-phase crystallization [14], aluminuminduced crystallization [15] or laser-beam crystallization [16]. Up to now, no satisfactory results could be achieved using these methods and therefore only few routes are still pursued. The concept of micromorph silicon tandem cells was introduced by the research group at the Institute for Microelectronics at the University of Neuchâtel [17]. The micromorph tandem structure is composed of a high-bandgap amorphous top and a low-bandgap intrinsic microcrystalline bottom layer, deposited by VHF-PECVD 5. Stable solar cell efficiencies of 10.7% and integrated module (24 cm 2 ) efficiencies of 9.8% have been achieved using a 2 µm bottom cell, demonstrating the potential of this concept [18]. Compared to a-si:h solar cells, the micromorph tandem cells feature an enhanced stability and the potential for higher efficiencies. Using a similar concept, the Kaneka research group achieved initial efficiencies of 14.5% for a 1 cm 2 solar cell and 12.3% for an integrated solar cell module with an aperture area of 3738 cm 2 [19]. However, only little details concerning deposition or recrystallization techniques and growth rates are disclosed. 3 PECVD: Plasma-Enhanced Chemical Vapor Deposition, IAD: Ion-Assisted Deposition, HWCVD: Hot-Wire Chemical Vapor Deposition. All silicon deposition techniques will be explained in the following chapter. 4 The notation of silicon crystal structures is classified according to the grain size: nanocrystalline (nc) with nm grain size, microcrystalline (µc) with 100 nm-1 µm grain size, polycrystalline with grain size exceeding 1 µm and multicrystalline (mc) with grain size in the mm and cm-range. 5 VHF-PECVD: Very High Frequency Plasma-Enhanced Chemical Vapor Deposition.

13 2.2 Thin Film Concepts High-temperature approach Temperatures up to the melting point of silicon can be applied within the high-temperature approach. This enables the use of fast silicon deposition techniques like APCVD and liquid-phase recrystallization e.g. by zone-melting, yielding large grain sizes in the mm or even cm-range. Moreover, conventional diffusion and metallization processes are feasible and common silicon solar cell technologies can be used. The large variety of solar cell concepts in the high-temperature approach can be classified according to the substrate in use. The need for high temperature stability restricts the choice of potential substrate materials to few candidates like low-cost silicon and high-temperature ceramics. Using low-cost silicon as substrate material the active silicon base layer can be deposited by epitaxy (epitaxial solar cell) at high temperatures. Potential low-cost silicon materials are e.g. reclaim wafers from microelectronic industry or cast metallurgical-grade (MG) silicon wafers. The epitaxial solar cell represents a silicon wafer equivalent which can be processed by conventional techniques and can therefore be directly introduced into standard industrial production lines, making this structure a very attractive concept. The preparation of epitaxial thin-film solar cells is one of the major subjects of this work and is therefore discussed in detail in chapter 6. Silicon deposition on foreign substrates results in a microcrystalline grain structure and the application of recrystallization steps to increase the grain size becomes indispensable. Low-cost substrates often inhibit high impurity concentrations and diffusion barriers between substrate and active silicon layer are necessary to prevent a contamination of the base layer. At the same time, the diffusion barrier can act as backside reflector, thereby increasing the optical path length and photocurrent generation. Using electrically conductive substrate and barrier layer, a conventional 2-side contact scheme can be applied. Otherwise, alternative contact designs have to be developed e.g. with both contacts located on the front side of the cell. The potential of this concept has been demonstrated by the Mitsubishi Electric Corporation, where an efficiency of 16.45% could be achieved for a silicon thin-film solar cell based on a recrystallized silicon layer on SiO 2 encapsulated silicon substrate [20]. The main drawbacks of the high-temperature approach is the lack in adequate high throughput silicon deposition reactors and the substrate and barrier layer question Transfer techniques The general concept of transfer techniques is based on the formation of a high-quality single-crystal silicon thin-film on a host-substrate by epitaxy, contact and emitter formation on the epitaxial layer, attachment of the epilayer to a mechanically supporting substrate and separation of the device from the host substrate. To make the transfer technique cost-effective, the host substrate has to be recycled to enable multiple use. Thin silicon films of excellent crystal quality can be prepared by this method and high efficiencies have already been demonstrated. Critical issues of this concept are the detachment procedure, recycling of the host substrate and the need for high throughput silicon deposition. The Epilift technique The Epilift concept has been introduced by the PV research group at The Australian National University (ANU). A single-crystal silicon wafer covered with a mesh-like oxide layer is used as host substrate. LPE is applied for silicon deposition and selective epitaxial growth occurs on the exposed

14 8 2 Crystalline Silicon Thin-Film (CSiTF) Solar Cells silicon area leading to an epitaxial silicon waffle-grid. Using an interdigitated grid design, solar cell processing is carried out with the epilayer still being attached to the substrate. The epilayer is detached from the substrate by laser cutting, wet-chemical etching or by applying a mechanical force. A detailed description of this method can be found in [21]. Efficiencies of up to 13% have been recently reported on a 1 cm 2 solar cell [22]. Porous silicon Several research groups focus on the application of single-crystal substrates with sacrificial porous layer for thin-film formation. In general, at least two layers of different porosity are formed on the substrate surface, with the top and bottom layer featuring low and high porosity respectively. Thermal annealing of the sample under hydrogen leads to a closing of the pores in the top porous layer, which is subsequently used as substrate for epitaxial deposition of a thin silicon film. After epitaxy, emitter contact formation is accomplished on the epilayer surface, a superstrate (usually glass) is attached to the surface and separation of the semi-finite device from the host wafer is done via the second, weak porous layer. After lift-off the host substrate can be reused. Using this approach, the research group at the Bavarian Center of Applied Energy Research (ZAE) introduced the Ψ-process (Ψ: psi for perforated silicon) [23] and the PSI-process (porous silicon) [24]. Solar cells based on so-called QMS-layers (quasi-monocrystalline, referring to the structure of the top porous layer) [25], [26] were presented by the Institute of Physical Electronics and the University of Stuttgart leading to efficiencies up to 16.6% for silicon thin-films transferred to glass superstrates [27]. Using a similar process route, the Sony Corporation (Japan) reported 12.5% efficiency for silicon films transferred to transparent plastic films [28].

15 3 Chemical vapor deposition (CVD) of silicon With the advent of silicon based electronic devices the deposition of silicon layers became a key technology in microelectronic production. Polycrystalline and especially epitaxial silicon layers are widely used e.g. in bipolar and MOS applications. Silicon thin-film solar cells are based on the use of a thin active silicon layer for photocurrent generation and therefore the deposition of silicon films on various substrate materials has also become a major issue in this research area. The silicon deposition techniques used for photovoltaic applications greatly benefit from the expertise in microelectronic industry. An overview on silicon deposition techniques and applications is given in this chapter. The principles of thermal CVD are explained in more detail in terms of transport phenomena and chemical reactions and common reactor designs for APCVD systems are presented. The chapter closes with a technical description of the APCVD systems developed at Fraunhofer ISE for photovoltaic applications. 3.1 Silicon deposition techniques For the deposition of silicon a large variety of techniques exists which can be roughly categorized by the silicon source in use. In liquid-phase epitaxy (LPE) a melt consisting of silicon and a metal solvent is used as silicon source. The deposition from vapor phase can be split up in two groups: physical vapor deposition (PVD) and chemical vapor deposition (CVD). Physical vapor deposition refers to techniques very similar to evaporation where solid silicon is transferred into the gas phase under high vacuum conditions. Solid-source molecular beam epitaxy (MBE) is the most prominent example to be mentioned in this context. Chemical vapor deposition denotes deposition processes which are based on chemical reactions with the silicon-containing reactants being supplied by a gaseous source. Common methods to activate the chemical reaction are thermal heating of the samples (resistive heating, radiofrequency induction, high-intensity lamps, lasers), plasma and catalytic activation. In plasmaenhanced chemical vapor deposition (PECVD) the activation energy is provided by thermal heating supported by plasma making depositions at low temperatures possible Liquid Phase Epitaxy (LPE) In silicon liquid-phase epitaxy a metal solvent saturated with silicon is used as silicon source. Solvents which are typically applied are indium (In) and tin (Sn) or other low-melting metals. Intentional doping of the growing layers is achieved by adding suitable dopants like gallium (Ga) for p-type and indium-phosphite (InP) for n-type layers from In melt. For silicon growth the solvent is heated and brought into contact with silicon bulk material thus producing a silicon saturated melt according to the phase-diagram. When saturation is reached the melt is cooled down resulting in a supersaturation. 9

16 10 3 Chemical vapor deposition (CVD) of silicon Silicon samples are introduced into the melt and excessive silicon crystallizes on the free silicon surface. Starting from temperatures well above 900 C the melt is slowly cooled down at rates in the range of few Kelvin per minute and below. The growth process takes place near thermal equilibrium with growth rates in the range of 1 µm/min. For LPE tipping boat or centrifugal systems are traditionally used [29]. Long process cycles and small wafer size capacity result in low throughput. The necessity for solvent metals of high purity (6N) represents a significant cost factor for this technology. Silicon LPE is mainly used in photovoltaic research applications Physical Vapor Deposition (PVD) Molecular Beam Epitaxy (MBE) Silicon deposition by MBE from a solid source is accomplished by electron beam evaporation of silicon in ultra-high vacuum (UHV). Ultra-pure silicon source materials have to be employed to keep the contamination level of the deposited films on a low level. Layer doping is achieved by coevaporation of dopant material e.g. aluminum (Al) for p-type and Ga or antimony (Sb) for n-type doping [30]. Silicon deposition by MBE can be performed in a wide temperature range, from room temperature to temperatures well above 500 C. For the growth of device-quality silicon epilayers, sample temperatures exceeding C have to be used. Typical growth rates are nm/min [30]. The most crucial issue in MBE is the necessity for very clean sample surface, reactor and vacuum conditions to grow high quality epilayers. MBE allows a low-temperature deposition of very thin films on a submicron-scale with sharp transition regions. Applications of MBE include e.g. silicon submicron devices, deposition of metal silicides or heteroepitaxy of thick strained SiGe layers on Si substrates. Ion-Assisted Deposition (IAD) Similar to MBE, solid silicon is evaporated by electron beam evaporation in IAD. About 1-5% of the evaporated silicon atoms are ionized and accelerated onto the substrate. Due to the kinetic energy of the ions, the substrates can in principle be maintained at lower temperatures for silicon deposition compared to MBE. In [31] epitaxial deposition at C with growth rates of µm/min are reported. In silicon thin-film solar cell R&D, IAD is used for the deposition of silicon films on lowtemperature substrates Chemical Vapor Deposition (CVD) Thermal Chemical Vapor Deposition Thermal CVD is based on the decomposition of silicon-containing source gases at the heated sample surface and subsequent incorporation of silicon atoms into the growing film. Thermal CVD can be carried out at different operation regimes depending on process temperature and pressure. Atmospheric pressure CVD (APCVD) operates at high deposition temperatures up to 1300 C where deposition rates up to 10 µm/min can be achieved. Trichlorosilane (SiHCl 3, TCS) highly diluted in hydrogen is typically used as silicon source gas. In-situ layer doping is achieved by adding suitable

17 3.1 Silicon deposition techniques 11 dopant gases, e.g. diborane (B 2 H 6 ) and phosphine (PH 3 ) diluted in hydrogen for p-type and n-type doping respectively. APCVD is in favor of epitaxial depositions because the high process temperature enables an optimal arrangement of deposited atoms in the silicon crystal matrix and crystals with extremely low defect densities can be grown. Typically, silicon epitaxy by APCVD is carried out in a temperature range of C. Compared to other deposition techniques, where high vacuums and therefore complex pumping systems are necessary, little technological effort is needed for CVD at atmospheric pressure and continuous systems are feasible. Most APCVD system can also be operated at reduced pressure (RPCVD). The deposition chemistry is identical to APCVD but the process pressure is reduced to approx Pa. Therefore epitaxial depositions can be carried out at lower temperatures without deterioration of crystal quality. Low-pressure CVD (LPCVD) is mainly applied for the deposition of polysilicon layers. The deposition of epitaxial silicon is also feasible but not widely used. SiH 4 typically serves as silicon source gas and B 2 H 6 and PH 3 as dopants. At deposition temperatures in the range of C and low pressures of Pa, polysilicon layers can be grown with deposition rates of 5-20 nm/min [33]. LPCVD is widely used in microelectronic industry for the deposition of polycrystalline silicon and amorphous materials [34]. Ultrahigh-vacuum CVD (UHV-CVD) is operated at still lower pressures than LPCVD ( Pa). A load-lock is necessary and turbo-molecular pumps are essential to reach the required vacuum. Ultraclean process conditions are mandatory to enable epitaxial layer growth. Compared to LPCVD the diffusivity of molecules is increased and depositions are possible at low temperatures, down to 550 C [34]. Similar to MBE, UHV-CVD allows an accurately controlled deposition of high quality, thin Si and SiGe epitaxial layers with extremely sharp transitions. Plasma-Enhanced Chemical Vapor Deposition (PECVD) PECVD is based on the dissociation of a silicon source gas in a plasma and subsequent deposition on a heated substrate. Radio frequency (RF) power in the MHz range is commonly used as excitation source. Sample temperatures below 400 C are feasible which enables the processing of temperature sensitive samples at low thermal budget. The operating pressures range from Pa and typically silane (SiH 4 ) is used as silicon source gas. Silicon epilayers may be grown but at lower quality compared to thermal CVD because of the reduced deposition temperature. PECVD allows the deposition of a large variety of materials with different properties. It is widely used for the deposition of dielectric layers, hydrogenated microcrystalline (µc-si:h) and amorphous (a- Si:H) silicon films. Hot-Wire CVD (HWCVD) In hot-wire or thermocatalytic (Cat) CVD SiH 4 is decomposed by a catalyst, usually a heated tungsten or tantalum wire in a low pressure ambient. During the deposition the substrate temperature is held at a constant level in the range of C. Amorphous and microcrystalline silicon layers can be deposited at rates up to 300 nm/min and 60 nm/min respectively. HWCVD has raised increasing interest in the past decade because this method allows the deposition of silicon films with improved electrical stability and at higher growth rates compared to PECVD.

18 12 3 Chemical vapor deposition (CVD) of silicon Applications in thin-film solar cells and thin-film transistors (TFTs) are currently under investigation [32] Overview on deposition techniques and applications The demand for a controlled deposition of epitaxial and polycrystalline silicon layers emerged from VLSI technology and applications. In microelectronic industry the focus for e.g. silicon epilayers is on perfect crystallinity, sharp doping transitions as well as thickness and doping uniformity. Sophisticated deposition techniques have been developed and optimized to accomplish these requirements. Today silicon deposition by CVD is state-of-the-art for all epitaxy processes used in microelectronic production. With the ever decreasing size of microelectronic devices and novel device designs, today s research activities focus on industrial feasible technologies for very thin epilayers deposited at low temperatures. Silicon deposition technologies have also become an important tool in silicon thin-film solar cell R&D for the formation of thin active base layers. Depending on the solar cell structure and especially on the substrate-type (see section 2.2) different silicon deposition techniques are applied. Similar to microelectronic devices the deposition technique is chosen according to the maximum temperature tolerable for device fabrication. T [ C] Liquid Source (LPE) Rate [µm/min] Si-source Si-film Ref. Applications LPE In solvent Epi-Si [35] RLPE In solvent Epi-Si [36] Epi-lift, epitaxial thin-film solar cells Solid Source (PVD) MBE > Solid Si Epi-Si [30] Submicron epitaxial silicon films IAD Solid Si Epi-Si [31] Silicon thin-film solar cells on glass, Ψ-process Vapor Source (CVD) LPCVD SiH 4 Poly-Si [37] Sensors, diodes, transistors, gate electrode in MOS devices, emitter/base contacts in bipolar devices SiH 2 Cl 2 Epi-Si [38], [39] Epitaxial thin-film solar cells APCVD SiHCl 3 Epi-Si This work SiHCl 3 Epi-Si [40] SiHCl 3 Epi-Si [41] Epitaxial thin-film solar cells, Thin-film solar cells on foreign substrates, QMS and PSI process, bipolar and MOS esp. CMOS applications PECVD SiH 4, SiF 4 µc-si:h, a-si:h [42] VHF- PECVD SiH 4 µc-si:h [43] a-si:h solar cells, micromorph tandem solar cells, sensors, thin film transistors HWCVD SiH 4 µc-si:h, a-si:h [44] Table 3.1: Overview on silicon deposition techniques and applications. 6 RLPE: Rapid LPE.

19 3.2 Deposition principle of silicon by thermal CVD 13 Table 3.1 gives an overview on the most commonly used silicon deposition techniques and main applications with emphasis on silicon solar cell R&D. 3.2 Deposition principle of silicon by thermal CVD The deposition of microcrystalline and epitaxial silicon layers by APCVD for silicon thin-film solar cells is the major subject of this work. This section aims to give an insight on the principles of silicon deposition by thermal CVD with main focus on TCS as silicon source gas. In order to predict deposition rates for a given reactor setup and therefore to optimize process parameters and reactor geometry, adequate growth rate models reflecting real conditions are needed. However, the description of the silicon growth process in CVD is a complex issue where gas transport phenomena have to be coupled to chemical reactions on the substrate surface and in the gas phase. A general model describing the entire deposition process involves the solution of many coupled partial differential equations. Because of the large complexity of the problem many authors restrict themselves to a simplified modeling of specific operating regimes e.g. by neglecting gas flow dynamics. The development of improved models and simulation tools is still a current topic of research [45], [46], [47] Transport The transport phenomena in fluid dynamics are generally described by simultaneously solving the basic equations for conservation of total mass, momentum, energy and chemical species in three dimensions with the process gas assumed to obey the ideal gas law and further assuming adequate boundary conditions [48], [49]. Neglecting all chemical reactions and temperature fields the transportproblem can be numerically solved for different reactor geometry. Taking into account radiation transport and temperature fields the problem is getting more complex due to the temperature dependence of most physical parameters (e.g. heat capacity, thermal diffusivity, gas density, viscosity etc.) determining the mass transport. The main effect on transport phenomena when chemical reactions are included is the local change in gas composition and therefore the change in all other parameters depending on this variable. Transport and reaction kinetics influence each other and a closed solution of the entire deposition problem can only be obtained if both phenomena are accounted for. For a more qualitative description of gas flow dynamics and to allow for an easy determination of the relevance of different transport phenomena without computational methods, dimensionless numbers (e.g. Reynolds, Damkoler, Peclet, Grashof numbers) have been introduced [50]. These numbers can be calculated from reactor geometry, gas phase composition and properties and depending on their value, conclusions about the gas transport behavior in the CVD reactor can be drawn Thermal equilibrium conditions Silicon CVD is traditionally based on the deposition from process gases composed of a silicon precursor and hydrogen carrier gas. In thermodynamic equilibrium the partial pressures of all species present in a gas mixture can be calculated using the Law of Mass Action. Considering e.g. a chemical reaction of two species A and B reacting to species C and D:

20 14 3 Chemical vapor deposition (CVD) of silicon aa + bb cc + dd (3.1) where the lower letters denote the stoichiometry constants. If the system is in equilibrium at a given temperature and pressure, then the value of c d [ C] [ D] K( T ) = a b (3.2) [ A] [ B] is constant. The values in square brackets correspond to the concentration of each specie and K denotes the equilibrium constant. Assuming an ideal gas the concentrations can be replaced by the corresponding partial pressure of each gas component. Calculation of the standard free energy change G 0 allows to predict whether a reaction will occur or not: 0 G = RT ln K (3.3) where R and T denote the gas-constant 7 and temperature respectively. The free energy change can be obtained from the standard state Gibbs free energies of formation which are listed in the JANAF tables [51]. For G 0 <0 the reaction under consideration occurs spontaneously, while in thermal equilibrium the change in standard free energy is zero. For a system containing several gas species the equilibrium composition can therefore be determined as a function of temperature if all possible chemical reactions and their equilibrium constants or Gibbs free energy changes are known. To calculate the partial pressures the free energy of the system has to be minimized [52]. The gas phase composition of a Si-H-Cl-system under atmospheric pressure was calculated at thermodynamic equilibrium using a software package [53] which refers to the JANAF tables. In Figure 3.1 the results are shown for two different Cl/H-ratios 8 with temperatures varied between 700 C and 1300 C. In commercial APCVD reactors Cl/H-ratios below 0.1 are typically applied, represented by the graph on the left-hand-side in Figure 3.1. In Figure 3.1 (right) the process conditions are set according to the standard epitaxy process used for the RTCVD100 reactor built at Fraunhofer ISE (see section 3.4.2). Considering the gas phase composition at low temperatures, SiHCl 3 and SiCl 4 dominate the gas composition for both process conditions. At high temperatures HCl and SiCl 2 are the most abundant species. For low Cl/H-ratios and temperatures above 1100 C SiCl 2 is clearly the dominating silicon containing compound whereas different silicon chlorides with similar mole fractions are present for high Cl/H-ratios at elevated temperatures. CVD does not occur at thermal equilibrium conditions and therefore the presented calculations do not represent the actual conditions in the CVD reactor. Nonetheless, some general information on possible effects of temperature on the gas phase composition can be drawn from these calculations. 7 Universal gas constant R=8.315 Jmol -1 K The Cl/H-ratio denotes the ratio of chlorine to hydrogen atoms in the gas phase. This ratio is constant throughout the deposition process since neither chlorine nor hydrogen are consumed or produced. Growthrelated phenomena often do not depend on gas flow rates but on the gas phase composition and the specification of the Cl/H-ratio to characterize the deposition conditions is more convenient.

21 3.2 Deposition principle of silicon by thermal CVD H 2 Cl/H = H HCl 10-1 SiCl 4 SiHCl 3 HCl Mole fraction SiCl 3 SiH 2 Cl 2 SiCl 2 SiHCl 3 SiCl4 Mole fraction SiCl 2 SiCl 3 Cl/H = 0.43 SiH 2 Cl SiH 3 Cl 10-4 SiH 3 Cl Temperature [ C] Temperature [ C] Figure 3.1: Equilibrium gas phase composition for a Si-H-Cl-system as a function of temperature for a total pressure of 1 atm calculated for different Cl/H ratios Reaction kinetics Figure 3.2 shows a simplified schematic model for silicon deposition from the gas phase. First, the precursor has to be transported from the main gas stream to the wafer surface (1). On the substrate surface, the precursor is adsorbed (2) and decomposed into a silicon adatom and reaction byproducts. While the silicon atom migrates on the substrate surface and is finally incorporated into the silicon crystal on an energetically favorable site (3), the byproducts are desorbed from the substrate surface (4). In addition to the deposition process, reactions in the gas phase can occur leading to particle generation, or the adsorbed silicon precursor molecule may be desorbed from the surface without being decomposed. Using chlorine containing silicon precursor gases, silicon etching by HCl is an important chemical side reaction. Hydrogen acts as a catalyst for the chemical decomposition process. The growth rate is determined by the supply of reactants and the velocity of the chemical reactions leading to the decomposition of the silicon precursor on the substrate surface. As already pointed out, both parameters depend on each other. Nonetheless some general statements on the temperature dependence of the growth rate can be made.

22 16 3 Chemical vapor deposition (CVD) of silicon Main gas stream Si 1 Byproducts Si 2 4 Si 3 Si Sample surface Figure 3.2: Simplified schematic of silicon deposition from a gaseous silicon source. Growth rate dependence on temperature For thermally activated reactions, the reaction rate mostly increases with rising temperature and the dependence of the reaction rate constant from temperature can be described by an Arrhenius function (assuming constant reactant concentrations and pressure) [37]: k E A = Aexp( ) (3.4) k T B Where k, A, E A, k B and T denote the reaction rate constant, collisional frequency, activation energy, Botzmann s constant and temperature. An Arrhenius plot based on experimental values can give information on the activation energy and on changes in reaction mechanisms determining the reaction rate. Figure 3.3 shows a typical Arrhenius plot for CVD at constant pressure. mass transport limited ln (growth rate) surface reaction limited Slope= -E A /k B 1/T Figure 3.3: Arrhenius plot for silicon CVD.