Digital Logic and Design (EEE-241) Lecture

Transcription

1 Digital Logic and Design (EEE-241) Lecture Dr. M. G. Abbas Malik edu Picture Source:

2 Previous lecture Introduction to design circuits with MSI and LSI Binary Adder BCD to Excess-3 BCD Converter BCD Adder Howe work: Magnitude Comparator 2

3 Decoder Discrete quantities of information are represented in a digital system with binary codes. A binary code of n-bits is capable of representing up to 2 n distinct elements of the coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. The decoder are called n-to-m line decoders where m 2 n 3

4 Decoder 2-to-4 Line Decoder x y D 0 D 1 D 2 D 3 D 3 = xy x D 2 = xy y D 1 = x y D 0 = x y Each output line D i corresponds to a minterm. Thus a decoder generates the 2 n minterms of n input variables.

5 Decoder 3-to-8 Line Decoder It can be used to build a binary to octal conversion circuit. 5 3-to-8 line decoder can be used in general to for decoding any 3-bit code to provide eight possible outputs, one for each code.

6 Decoder BCD-to-Decimal Decoder It is 4-to-10 decoder because BCD code contain 4 binary digits to code a decimal digit and there are 10 decimal digit. With 4-bit inputs we can represent 16 different codes, so the 6 combinations are Don t Care conditions during the design procedure. 6

7 Decoder BCD-to-Decimal Decoder Map of simplification wx\yz D 0 D 1 D 3 D 2 01 D 4 D 5 D 7 D 6 11 X X X X 10 D 8 D 9 X X D 2 = x yz D 9 = wz 7

8 Decoder BCD-to-Decimal Decoder 8

9 Decoder Combinational Logic Implementation A decoder provides the 2 n minterms of n inputs. Any Boolean function can be expressed in sum of minterms (canonical form), one can use a decoder to generate the minterms and an external OR gate(s) to form the sum. A combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder and m OR gates. 9

10 Decoder Combinational Logic Implementation Example: Full-Adder S(x, y, z) = Σ(1, 2, 4, 7) C(x, y, z) = Σ(3, 5, 6, 7) x y z S C 10

11 Decoder with enable Some IC decoders are constructed with NAND gates. Since NAND gate produces the AND operation with an inverted output, it becomes more economical to generate the decoder minterms in their complemented form. Most, if not all, IC decoders include one or more enable inputs to control the circuit operation. 11

12 Decoder with enable Circuit diagram and Truth Table E x y D 0 D 1 D 2 D 3 1 X X

13 Decoder with enable Block diagram 13

14 Decoder Demultiplexer A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 n possible output lines. A decoder with an enable input can function as a demultiplexer. The selection of specific output line is controlled by the bit values of n selection lines. 14

15 Decoder Demultiplexer E is taken as a data input line Lines A and B are taken as the selection lines Exercise: Draw the circuit diagram for this 1-to-4 demultiplexer. 15

16 Decoder x y E 1-to-4 Demultiplexer: Circuit Diagram D 3 = xy D 2 = xy D 1 = x y D 0 = x y A decoder with an enable input is referred as a decoder/demultiplexer It is the enable input that t makes the circuit it a demultiplexer The decoder itself can use AND, OR, NAND or NOR gates. 16

17 Decoder Decoder circuits can be connected together to form a larger decoder circuit. 4-to-16 Decoder designed d with 2 3-to-8 decoders 17

18 Encoder 18 An encoder is a digital function that produces a reverse operation from that of a decoder. An encoder has 2 n (or m 2 n ) input lines and n output lines. The output lines generate the binary code for the 2 n input variables to-3 encoder

19 Encoder 8-to-3 Encoder to-3 4 encoder

20 Encoder 8-to-3 Encoder Truth Table Inputs Outputs D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 x y z

21 Multiplexer Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines and n selection lines whose bit combinations determine which input is selected. 21

22 Multiplexer 4-to-1 Multiplexer Input lines to-1 Multiplexer Output lines Select lines 22

23 Multiplexer 8-to-1 Multiplexer Input lines to-1 Multiplexer Output lines Select lines 23

24 Multiplexer Self Study How we can implement Boolean function using encoders and multiplexers? Chapter 5: Decoder, Encoders and Multiplexers l 24