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1 Is Now Part of To learn more about ON Semiconductor, please visit our website at ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

2 AN-684 Fairchild Semiconductor Application Note February 1990 Revised May Four-Stage Counter/Shift Register INTRODUCTION Many system designs require bi-directional counting and shifting functions. In most cases these functions are separate and unique requirements within the system design. For this reason, separate catalog parts are available. In some cases however, there is a requirement to have a device that will allow both counting and shifting functions. This is especially true in arithmetic, timing, sequential, or communication applications. Fairchild offers a very versatile counter/shift register in the This application note describes its function in detail and offers some simple uses. DESCRIPTION The contains four synchronous, presettable flipflops. Synchronous operation is provided by having all flipflops clocked simultaneously so that all output changes coincide. This mode of operation eliminates counting spikes on the outputs which are normally associated with asynchronous counters. The clock input is buffered and triggers the four flip-flops on the rising (positive-going) edge. The counters are fully programmable allowing the outputs to be set to either a HIGH (1) or LOW (0). As presetting is synchronous, setting low levels on the select inputs (S 0 -S 2 ) (see Table 1) disables the counter and causes the outputs to agree with the parallel inputs (P 3 P 0 ) on the next rising edge of the clock. Loading is accomplished regardless of the levels of the two enables (CEP, CET). TABLE 1. Function Select Table S 2 S 1 S 0 Function L L L Parallel Load L L H Complement L H L Shift Left L H H Shift Right H L L Count Down H L H Clear H H L Count Up H H H Hold The features both synchronous and asynchronous clear functions. The synchronous clear is performed by setting a binary five (101B) at the select inputs. On the next rising edge of the clock, the outputs will be forced LOW (0000) regardless of the levels at the enable inputs. A buffered asynchronous master reset (MR) is provided to clear all outputs LOW (0000) regardless of the levels of the clock, select, or enable inputs. Count up/count down functions are selected with the select inputs (S 2 S 0 ). These are synchronous operations and the outputs will increment/decrement in value on the rising edge of the clock. Both count enable inputs (CEP, CET) must be true (LOW) to count. The terminal count output (TC) becomes active-low when the count reaches zero in the DOWN mode or fifteen in the UP mode. Its duration is approximately equal to one period of the clock. The TC output is not recommended for use as a clock or synchronous reset for flip-flops. See Figure 1 for timing relationships in UP/DOWN counting. In simple ripple-carry cascading applications the terminal count TC is fed forward to enable the trickle enable (CET) input. This method is increasingly inefficient as the counting chain lengthens. The upper limit of the clock frequency is determined by the clock-to-terminal-count delay of the first stage, the cumulative trickle-enable (CET)-to-terminalcount delay of the intermediate stages, and the trickleenable-to-clock delay of the last stage. For faster counting rates a carry-lookahead scheme is necessary. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to change over from MAX to MIN in the UP mode, or from MIN to MAX in the DOWN mode. Since the final count cycle takes 16 clocks to complete, there is ample time for the ripple to propagate through the intermediate stages. The critical timing that limits the counting rate is the clockto-terminal-count of the first stage plus the parallel-enableto-clock (CEP) setup time of the last stage. Figure 2 shows the connections for the fast-carry counting scheme. AN Four-Stage Counter/Shift Register 2000 Fairchild Semiconductor Corporation AN

3 AN-684 TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES Illustrated below is the following sequence: 1. Clear outputs to zero. 2. Load (Preset) to binary thirteen. 3. Count up to fourteen, fifteen, carry, zero, one, and two. 4. Count down to one, zero, borrow, fifteen, fourteen, and thirteen. 5. Inhibit counting. Note: A MR overrides enables, data, and count inputs. FIGURE Used as Binary Up/Down Counter FIGURE 2. Fast Carry Counting Scheme 2

4 TYPICAL CLEAR, LOAD, AND COUNT SEQUENCES (Continued) Shift right/left modes are performed by making the appropriate selection on the selection inputs (S 2 S 0 ). Each rising edge of the clock will cause the outputs to shift once in the direction which is selected. For shift-left operation, input D 3 is used as the serial input. For shift-right operation, input CET/D 0 is used as the serial input. During shift operation the terminal count output reflects the level at the Q 3 output and the enables are don't cares. See Figure 3 for shift operation timing relationships and shift sequences. The provides two special modes of operation. The complement mode performs a one's complement of the outputs (Q 3 Q 0) on the rising edge of the clock input regardless of the levels at the enable inputs. The hold feature is asynchronous and simply stops counting or shifting operations. Both complement and hold are performed with proper selection of the select inputs. For a complete truth table of the operation, refer to Table 2. DESIGN CONSIDERATIONS Presetting the parallel inputs (P 3 P 0) may require a mixture of HIGH's and LOW's. A LOW may be preset by leaving the respective input open as the has a 50 kω resistor to V EE on the parallel inputs. A HIGH must never be made by tying the input to V CC /V CCA. This saturates the input transistor. Instead the input is set at a diode drop below V CC /V CCA for a preset HIGH. See Applications Note 682. Unused output pairs (Q n /Q n ) may be left unterminated. However, unused single outputs should be terminated to balance current switching in the outputs. For further details on system design considerations refer to the F100K ECL Design Guide. For AC/DC performance specifications and critical timing parameters refer to the datasheet. APPLICATIONS Figure 4 and Figure 5 demonstrate the use of the as UP/DOWN BCD counters. One additional gate is required to detect the limit count. Notice the alternate gate methods in Figure 4. The shows the classical AND/ NAND design similar to TTL and the shows the OR/NOR design of ECL. Figure 6 incorporates the use of a triple D-type flipflop. By using one stage of the , a 50/50 duty cycle can be realized from the divider. An 8-bit parallel-to-serial shifter can be constructed by cascading two 's as shown in Figure 7. The third counter reloads another 8-bit data word after eight serial counts. AN

5 AN-684 TYPICAL, CLEAR, LOAD, AND COUNT SEQUENCES Illustrated below is the following sequence: 1. Clear outputs to zero. 2. Load (preset) to binary twelve. 3. Shift-left using D 3 as serial input. 4. Shift-right using CET/D 0 as serial input. Note: In shift-right mode TC follows the Q 3 output. Note: In shift-left mode TC follows the D 3 input. Note: CEP is a don't care during shifting. FIGURE Used as Bi-Directional Shift Register 4

6 TRUTH TABLE Q 0 = LSB TABLE 2. Truth Table Inputs Outputs MR S 2 S 1 S 0 CEP D 0 /CET D 3 CP Q 3 Q 2 Q 1 Q 0 TC Mode L L L L X X X P 3 P 2 P 1 P 0 L Preset (Parallel Load) L L L H X X X Q 3 Q 2 Q 1 Q 0 L Invert L L H L X X X D 3 Q 3 Q 2 Q 1 D 3 Shift Left L L H H X X X Q 2 Q 1 Q 0 D 0 Q 3 Shift Right (Note 1) L H L L L L X (Q 0 Q 3 ) minus 1 1 Count Down L H L L H L X X Q 3 Q 2 Q 1 Q 0 1 Count Down with CEP not active L H L L X H X X Q 3 Q 2 Q 1 Q 0 H Count Down with CET not active L H L H X X X L L L L H Clear L H H L L L X (Q 0 Q 3 ) plus 1 2 Count Up L H H L H L X X Q 3 Q 2 Q 1 Q 0 2 Count Up with CEP not active L H H L X H X X Q 3 Q 2 Q 1 Q 0 H Count Up with CET not active L H H H X X X X Q 3 Q 2 Q 1 Q 0 H Hold H L L L X X X X L L L L L H L L H X X X X L L L L L H L H L X X X X L L L L L H L H H X X X X L L L L L Asynchronous H H L L X L X X L L L L L Master Reset H H L L X H X X L L L L H H H L H X X X X L L L L H H H H L X X X X L L L L H H H H H X X X X L L L L H AN = L if Q 0 Q 3 = LLLL H if Q 0 Q 3 LLLL 2 = L if Q 0 Q 3 = HHHH H if Q 0 Q 3 HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition Note 1: Before the clock, TC is Q 3 After the clock, TC is Q2 FIGURE 4. BCD Up Counter (0 9) 5

7 AN-684 FIGURE 5. BCD Down Counter (9 0) FIGURE 6. Divide by Five FIGURE 7. 8-Bit Shift Left 6

8 AN Four-Stage Counter/Shift Register Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

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