DESIGN OF BASIC SEQUENTIAL CIRCUITS USING REVERSIBLE LOGIC

Transcription

1 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) DESIGN OF BASIC SEQUENTIAL CIRCUITS USING REVERSIBLE LOGIC Rohini H Dr. Rajashekar S Dr. PriyatamKumar Electronics & Communication Electronics & Communication Electronics & Communication BVBCET BVBCET BVBCET Hubli, India Hubli, India Hubli, India rohini_sh@bvb.edu raj@bvb.edu priyatam@bvb.edu Abstract Reversible logic is an emerging research area. Its ability to reduce the power dissipation has made these circuits lossless circuits. Irreversible circuits or classical circuits have energy dissipation is proportional to the number of bits lost during computation. The reversible circuits do not lose information and can generate unique outputs from specified inputs and vice versa. It has application in diverse fields such as low power CMOS design, optical information processing, cryptography, quantum computation and nanotechnology. This paper proposes a reversible design of Flip Flops, Counters and Universal shift register. Universal shift register is an important memory element of the sequential circuit family. In this paper we proposed efficient design of reversible universal shift register that is optimized in terms of quantum cost, delay, garbage outputs. Each module has been coded using Verilog then simulated using Modelsim and prototyped in Xilinx-Spartan 3. Keywords Reversible, Garbage, Quantum cost I. INTRODUCTION Energy dissipation is one of the major issues in present day technology. Energy dissipation due to information loss in high technology circuits and systems constructed using irreversible hardware was demonstrated by R. Landauer in the year According to Landauers principle, the loss of one bit of information lost, will dissipate kt*ln (2) joules of energy where, k is the Boltzmanns constant and k=1.38x10-23 J/K, T is the absolute temperature in Kelvin [1]. The primitive combinational logic circuits dissipate heat energy for every bit of information that is lost during the operation. This is because according to second law of thermodynamics, information once lost cannot be recovered by any methods. In 1973, Bennett, showed that in order to avoid ktln2 joules of energy dissipation in a circuit it must be built from reversible circuits [2]. According to Moores law the numbers of transistors will double every 18 months. Thus energy conservative devices are the need of the day. The amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation. Reversible circuits are those circuits that do not lose information. The most prominent application of reversible logic lies in quantum computers [3]. A quantum computer will be viewed as a quantum network composed of quantum logic gates, it has applications in various research areas such as Low Power CMOS design, quantum computing, nanotechnology and DNA computing. Reversible computation in a system can be performed only when the system comprises of reversible gates. A circuit/gate is said to be reversible if the input vector can be uniquely recovered from the output vector and there is a one-to-one correspondence between its input and output assignments [4-5].The main challenges of designing reversible circuits are to reduce the number of gates, garbage outputs, constant inputs and quantum cost. While designing the proposed universal shift register, we optimized the quantum cost and number of garbage outputs of the proposed design. A. Basic Definitions pertaining to reversible logic Reversible logic gate : Reversible Gates are circuits in which number of outputs is equal to the number of inputs and there is a one to one correspondence between the vector of inputs and outputs [7]. It not only helps us to determine the outputs from the inputs but also helps us to uniquely recover the inputs from the outputs Constant inputs : This refers to the number of inputs that are to be maintaining constant at either 0 or 1 in order to synthesize the given logical function [8]. Garbage outputs : Additional inputs or outputs can be added so as to make the number of inputs and outputs equal whenever necessary. This also refers to the number of outputs which are not used in the synthesis of a given function. Garbage is the number of outputs added to make an n-input k-output function reversible. We use the words constant inputs to /16/$ IEEE

2 denote the present value inputs that were added to an (n:k) function to make it reversible. The following simple formula shows the relation between the number of garbage outputs and constant inputs. Input + constant input = output + garbage. [6] Quantum cost : Quantum cost refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. The quantum cost of a circuit is the minimum number of 2*2 unitary gates to represent the circuit keeping the output unchanged. The quantum cost of a 1*1 gate is 1 and that of any 2*2 gate is the same, which is 1 [10]. So, the quantum cost of a 2*2 Feynman gate is 1. Again, the quantum cost of a 3*3 Toffoli, Fredkin, Peres and New gate is 5, 5, 4 and 11 respectively [11][12][13]. TABLE I. List Of Reversible Gates Reversible Size Quantum Functionality Gates cost NOT 1X1 1 P=A CNOT(Feynman) 2X2 1 P=A Q=AxorB Fredkin 3X3 5 P=A Q=A B+AC R=AB+A C Toffoli 3X3 5 P=A Q=B R=ABxorC Pears 3X3 4 P=A Q=AxorB R=AB xor C Double Feynman 3X3 2 NG 3X3 11 P=A Q=AB xor C R=A C xor B Fig. 1. Methodology A. SEQUENTIAL CIRCUITS USING REVERSIBLE GATES Fig. 2. Fredkin gate II. IMPLIMENTATION METHODOLOGY In order to design the sequential circuits, the conventional logic gates are appropriately designed from the reversible gates. The reversible gates used to design the conventional logic are so chosen to minimize the number of reversible gates used and garbage outputs produced. List of reversible gates and their functionality is shown in talbe I. Figure 2 shows fredkin gate definition and Figure 3 shows the how AND operation is realized using Fredkin gate. Figure 4 shows the realization of OR function using fredkin gate. Feynman Gates can be used for copying the outputs and to avoid the fan out problem in reversible logic[8]. In the Feynman gate, there are exactly two outputs corresponding to the inputs and a 0 in the second input will copy the first input to both the outputs of that gate. Hence it can be concluded that Feynman gate is the most suitable gate for single copy of bit since it does not produces any garbage output Fig 3. Fredkin gate as AND gate Fig.4. Fredkin gate as OR gate

3 B. RS FLIP FLOP The clocked RS flip flop consists of a basic NOR and AND gates. Figure 5 shows the RS flip flop designed from conventional irreversible gates. Figure 6 shows the RS flipflop designed from the reversible equivalent gates. Fig.7. Conventional D FLIP FLOP Fig.5. Conventional SR FLIP FLOP Fig.8. Reversible D FLIP FLOP Fig.6. Reversible SR FLIP FLOP The proposed circuit of the flip flop is evaluated in terms of number of reversible gates used and garbage outputs produced. Table II shows the evaluation of the proposed RS flip flop. TABLE II. Comparison w.r.t RS FF Fig.9. Reversible D FLIP FLOP The proposed circuit of the flip flop is evaluated in terms of number of reversible gates used and garbage outputs produced. TableIII shows the evaluation of the proposed D flip flop. Table III. Comparison w.r.t D FF C. D FLIP FLOP The D flip flop is a modification of the clocked RS flip flop. In the D flip flop, the D input goes directly to the S input and its complement is applied as an R input. Figure 7 shows the D flip flop designed from irreversible gates. Figure 8 shows the D flip flop designed from the reversible equivalent gates. Figure 9 shows proposed reversible DFF using 2X2 CNOT gate having quantum cost of only 1.

4 D. UP COUNTER The counter is one of the most intensively used functional devices in digital systems. The counter is basically a group of flipflops connected together in such a way that the combined output will perform the counting operation. The reversible design of the 4-bit Up-Counter is shown in Figure 10. At the output of each reversible D Flip- op, the complemented Q output is produced using Feynman Gate with the input B=1. These complemented Q outputs of each D Flipflop reversible design performs the Up-Counter operation. Fig.11. Block diagram of Universal shift register1 Fig.10. Reversible UP COUNTER TABLE IV. Comparison w.r.t Universal Shift Register III. Each D Flipflop contains 1 reversible gate, 1 constant input and 0 garbage output. Hence the proposed reversible counter design contains 4 reversible gates, 4 constant inputs and produces 0 garbage output. DESIGN OF REVERSIBLE UNIVERSAL SHIFT REGISTER In this section we presented novel designs of reversible universal shift register and its components that are optimized in terms of quantum cost and garbage outputs. A. Proposed Universal Shift Register 1 Universal shift registers store binary data and can be shifted left or right when a clock signal is applied. All modes of operation such as serial-in serial-out (SISO), parallel-in parallel-out (PIPO) are performed upon the occurrence of clock. Figure11 shows our proposed universal shift register consists of 4 D flipflop blocks and one 1 to 4 demultiplexer. The multiplexer have two common selection inputs S1 and S0. Input 0 in each multiplexer is selected when SIPO-LEFT = 00, when SIPO-RIGHT =01, when SISO-LEFT = 10, when SISO-RIGHT =11 the present value of the register is applied to the D inputs of the flip flops. This condition forms a path from the output of each flip flop into the input of the same flipflop so that the output recalculates to the input in this mode of operation. B. Proposed Universal Shift Register 2 The universal shift register store binary data and its data can be shifted left or right when a clock signal is applied. All modes of operation such as SISO (serial-in-serial output), SIPO (serial-in-parallel output), PISO (parallelin-serial output) and PIPO (parallel-in-parallel output) can also be performed upon the occurrence of clock. TABLE V. Modes of Universal Shift Register Figure 12 shows the propose universal shift register. Thus, serial data parallel data can be loaded into shift register. The values of the select lines determine the operation to be performed as given in table 5. The existing design of Reversible Universal Shift Register in reference [24] is basically built from basic cells comprising of DFF, Feynman gate (FG) and Fredkin gates. In the existing design fan-out circuits are not used for any of the signals. The four multiplexers have two common selection inputs S1 and S0.Input 0 in each multiplexer is selected when S1S0 = 00, input 1 is

5 selected when S1S0 = 01 and similarly for other two inputs. Fig.14. D FLIP FLOP Fig bit COUNTER Fig.12. Block diagram of Universal shift register2 The proposed design of Universal Shift Register shown in Figure 12 consist of flip flops blocks using Master slave D FF, D FF with synchronous or asynchronous set/rest and 4:1 Multiplexer design. IV. RESULTS AND DISCUSSIONS SR Flip Flop based on reversible logic simulation waveform shown in Figure 13. When clock is high the then the operation of SR Flip Flop is enable when SR inputs are 00 output Q is 0, SR=01 output Q=0, SR=10 output Q=1 and output Qb= Q. When the clock is low outputs not responding to inputs. Universal shift registers store binary data and can be shifted left or right when a clock signal is applied. Simulated waveforms of universal shift register shown in Figures 16,17,18 and 19. Fig.16. SIPO-LEFT Universal shift register Fig. 13. SR Flip Flop D Flip Flop based on reversible logic simulation waveform shown in Figure 14. When clock is high the then the operation of D Flip Flop is enable when output follows the input and output Qb= Q. When the clock is low outputs not responding to input. 4bit Up-counter using eversible D Flip Flops simulation waveform shown in Figure 15. When clock is high the then the operation of Counter is enable to count the 4bit data when output is 1111 then it reset to 0000, again counting is started. Fig.17. SIPO-RIGHT Universal shift register All modes of operation such as serial-in serial-out (SISO), parallel-in parallel-out (PIPO) can also be performed upon the occurrence of clock. Figure shows our proposed universal shift register consists of 4 D flip flop blocks and four 4-to-1 Demultiplexer Fig.18. SISO-LEFT Universal shift register

6 The multiplexer have two common selection inputs S1 and S0. Input 0 in each multiplexer is selected when SIPO- LEFT = 00, when SIPO-RIGHT =01, when SISO-LEFT = 10, when SISO-RIGHT =11 the present value of the register is applied to the D inputs of the flip flops. This condition forms a path from the output of each flip flop into the input of the same flip flop, so that the output recalculates to the input in this mode of operation. outputs ACMJournal of Emerging Technologies in Computing Systems, vol. 6, no.4, Article 14, pp. 14:114:35, Dec [9] J.Smoline and David P.DiVincenzo, \Five two-qubit gates are su cient to implement the quantum fredkin gate Physics Review A, vol. 53, no.4, pp ,1996. [10] Yang G., Song X, Hung WNN, and Marek Perkowski, \Bidirection Synthesis for Reversible circuits IEEE Computer Society Annua; Sym-posium on VLSI New Frontiers in VLSI Design, [11] D. Maslov and G.W. Dueck, \Reversible cascades with Minimal Garbage IEEE Transactions on CAD, vol. 23(11), pp , November [12] Richard P.Feynman, \Quantum mechanical computers Foundations of Physics, vol.16, no. 6, pp ,1986. Fig.19. SISO-RIGHT Universal shift register V. CONCLUSION In this paper a novel design of RS and D Flip Flops,4 bit up counter and reversible universal shift register using reversible logics are proposed. A feynman gate that acts as a D Flip Flop is proposed in this paper whose quantum cost is one. The proposed design can also be extended to a 4-bit Reversible Universal shift Register. The proposed design is realized using Xilinx ISE14.2 and shows reduction in. quantum cost and garbage outputs. References [1] R. Landauer, \Irreversibility and Heat Generation in the Computational Process, IBM Journal of Research and Development, 5, pp , [2] C.H. Bennett, \Logical Reversibility of Computation,IBM J.Research and Development, pp , November [3] Vlatko Vedral, Adriano Bareno and Artur Ekert, \QUANTUM Net-works for Elementary Arithmetic Operations, arxiv:quantph/ v1, nov [4] A. Mishchenko, M. Azad Khan, A. Coppola, S.Yanushkevich, \A gen-eral decomposition for reversible logic IEEE transactions Proc. RM2001, Starkville, pp: , [5] Ha z Md. Hasan and A.R. Chowdhury, \Design of Reversible Binary Coded decimal Adder by using Reversible 4 bit Parallel Adder, IEEE Trans. Very Large Scale Integr. (VLSI) Jan [6] B.Raghu kanth, B.Murali Krishna, M. Sridhar, \A DISTINGUISH BE-TWEEN REVERSIBLE AND CONVENTIONAL LOGIC GATES, In-ternational Journal of Engineering Research and Applications (IJERA) ISSN: Vol. 2, Issue 2,Mar-Apr 2012, pp [7] Abu Sadat Md. Sayem, Masashi Ueda, \Optimization of reversible se-quential circuits Journal of Computing Volume 2, Issue 6, June 2010, ISSN [8] H.Thapliyal and N. Ranganathan, \Design of reversible sequentialcir-cuits optimizing quantum cost, delay and garbage [13] H. Thapliyal and M. B. Srinivas, \A Beginning in the Reversible Logic Synthesis of Sequential Circuits Proceedings of Military and Aerospace Programmable Logic Devices International Conference, [14] SKS Hari, S Shro, \E cient Building Blocks for Reversible Sequential Circuit designproceedings of the International Midwest Symposium on Circuits and Systems, [15] J.E. Rice, \A New Look at Reversible Memory ElementsProceedings of IEEE International Symposium on Circuits and Systems, [16] V. Rajmohan, \ Design of Counters Using Reversible LogicMember IACSIT IEEE [17] H. Thapliyal and A. P. Vinod, \Design of reversible sequential elements with feasibility of transistor implementationin Proc. the 2007 IEEE Intl. Symp. On Cir.and Sys., pages , New Orleans, USA, May [18] Ashis Kumer Biswas, La fa Jamal, M. A. Mottalib1, Ha z Md. Hasan Babu, \Design of a Reversible Parallel Loading Shift RegisterDhaka Univ. J.Eng and Tech. vol 1(2) 1-5,2011. [19] D. Krishnaveni, M. Geetha Priya, \A Novel Design of Reversible Uni-versal Shift Register with Reduced Delay and Quantum CostJournal of Computing, Volume 4, Issue 2, February 2012, Issn l [20] 1Md. Selim Al Mamun, 2Indrani Mandal, 3Md. Hasanuzzaman, \De-sign of Universal Shift Register Using Reversible Logic IJET Publica-tions UK. All rights reserved September, [21] Himanshu Thapliyal and M.B Srinivas, \ A Beginning in the Reversible Logic Synthesis of Sequential CircuitsMAPLD 2005 [22] Md. Belayet Ali 1, Md. Mosharof Hossin1 and Md. Eneyat Ullah1, \Design of Reversible Sequential Circuit Using Reversible Logic Synthe-sisDecember 2011 [23] Raghava Garipelly1, P.Madhu Kiran2, A.Santhosh Kumar, \A Review on Reversible Logic Gates and their ImplementationVolume 3, Issue 3, March 2013 [24] Rashid Anwar et al, \A Novel Design of Reversible Universal Shift Reg-isterInternational Journal of Computer Science and Mobile Computing, Vol.3 Issue.3, March- 2014, pg