High-K K Dielectric Materials In Microelectronics

Transcription

1 High-K K Dielectric Materials In Microelectronics NAME: Neha Tomar IIT GUWAHATI

2 INTRODUCTION OUTLINE MOORE S S LAW AND TRANSISTOR SCALING WHY HIGH-K K DIELECTRICS? APPLICATIONS IN MICROELECTRONICS HIGH-K K DIELECTRICS IN DRAMS HIGH-K K GATE DIELECTRICS SUMMARY

3 INTRODUCTION MOORE S S LAW A prediction made by Mr. Gordon Moore that the number of transistors on a chip double every two years.

4 INTRODUCTION Transistor physical gate length will reach ~15nm before end of this decade, and ~10nm early next decade

5 INTRODUCTION PROBLEM AS TRANSISTOR IS MADE SMALLER. Gate dielectric,silicon dioxide are only a few atomic layers thick now. Leakage current increases, as thickness decreases. A New dielectric material is needed to reduce leakage current. HIGH-K K DIELECTRICS IN MICROELECTONICS

6 INTRODUCTION WHAT ARE HIGH-K MATERIALS? Thicker class of material known as High-K is likely to replace Silicon oxide. K stands for dielectric constant, a measure of how much charge a material can hold. HIGH-K K DIELECTRICS IN MICROELECTONICS

7 INTRODUCTION HIGH-K MATERIAL BENEFITS Sio2 High-k Capacitance 1* 1.6* Leakage 1* < 0.01* HIGH-K K DIELECTRICS IN MICROELECTONICS

8 HIGH-K GATE STACKS TRANSISTOR A simple switch Current flows source to drain when a certain Voltage is applied on The gate, otherwise Doesn t flow. Schematic of important regions Of field effect transistor gate stack

9 HIGH-K GATE STACKS Scaling limits for current Gate Dielectrics Silicon dioxide is current gate dielectrics Sio2 thickness can t be decreased less than 1-1.5nm, because leakage current increases So, Continual scaling. will require high-k material for dielectric layer.

10 HIGH-K GATE STACKS ALTERNATIVE HIGH-K GATE DIELECTRICS Metal oxides of ZrO2, HfO2, Y2O3 and Al2O3 High-K material Dielectric constant Leakage Current reduction Thermal stability Tmax c ZrO2 ~23 * ~900 HfO2 ~20 * ~950 Y2O3 ~15 * Silicate formation Al2O3 ~10 * ~1000

11 HIGH-K GATE STACKS ALTERNATIVE HIGH-K GATE DIELECTRICS Pseudo binary materials (HfO2) x (SiO2) 1-x and (ZrO2) x (SiO2) 1-x Silicate-Si interface is chemically similar to the SiO2-Si Interface. Low defect densities Hf-silicate between Si layer

12 HIGH-K GATE STACKS ALTERNATIVE HIGH-K GATE DIELECTRICS Pseudo binary materials (HfO2) x (SiO2) 1-x and (ZrO2) x (SiO2) 1-x Silicate-Si interface is chemically similar to the SiO2-Si Interface. Low defect densities Hf-silicate between Si layer

13 HIGH-K GATE STACKS KEY GUIDELINES FOR SELECTING AN ALTERNATIVE GATE DIELECTRIC Interface quality Permittivity and band gap Thermodynamic stability Compatibility with the current or expected materials to be used in processing for CMOS devices Reliability

14 HIGH-K GATE STACKS PROCESS ISSUES THAT AFFECT DEVICE Pre-deposition treatments HF last,o 3 etc. Pre/post-deposition annealing O 2 and N 2 annealing etc. High-k deposition ALD,CVD etc. Gate electrode metal gates, poly-silicon gates etc.

15 HIGH-K GATE STACKS GATE ELECTRODE PROBLEMS WHEN SiO2 IS REPLACED WITH HIGH-K Problems arise due to interaction with the Poly-Si gate Phonon Scattering electrons slow down Threshold voltage pinning-due to defects that arise at the gate-dielectric/gate electrode

16 HIGH-K DIELECTRICS IN DRAMS GATE ELECTRODE SOLUTION-METAL GATE

17 HIGH-K GATE STACKS STATE-OF-THE-ART TRANSISTOR Metal gate and high-k dielectric transistor offer the promise toward CMOS Technology nodes. Other technologies are also emerging for low-power and high-performance logic. For example Nanoelectronic devices, SOI, double gate and tri-gate etc.

18 HIGH-K DIELECTRICS FOR DRAMS WHAT IS DRAM? DRAM is a type of random access memory that stores each bit of data in a separate capacitor.

19 HIGH-K DIELECTRICS FOR DRAMS The continuous shrinking technology up to Gbit density exposes many challenges. Sio2 can not be made thinner any more. Alternative dielectric having a substantially higher permittivity is needed for further high density DRAMs.

20 HIGH-K DIELECTRICS FOR DRAMS ALTERNATIVE HIGH-K DIELECTRICS FOR DRAMS Among this, BST film is the most promising capacitor material in future DRAM applications.

21 HIGH-K DIELECTRICS FOR DRAMS BST capacitor structure with the stacked barrier scheme. Cross-section TEM Image of a stacked-capacitor Structure with a BST dielectric Pt electrode and a TaSiN barrier layer. Minimum feature size=0.2um Dielectric thickness=27 nm

22 HIGH-K DIELECTRICS FOR DRAMS Factors that influence BST thin film properties Processing methods Film composition Crystalline structure Microstructure Surface morphology Film thickness

23 HIGH-K DIELECTRICS FOR DRAMS Process Integration Main Points BST deposition techniques Electrode material & Barriers

24 HIGH-K DIELECTRICS FOR DRAMS Process Integration BST deposition techniques Main techniques MOCVD rf-sputtering

25 HIGH-K DIELECTRICS FOR DRAMS Process Integration ELECTRODE MATERIAL Noble metals Exp-Pt, Ru etc Low leakage current Conducting Oxides Exp-Iro 2 etc High leakage current

26 HIGH-K DIELECTRICS FOR DRAMS Process Integration Various integration schemes for BST capacitor

27 HIGH-K DIELECTRICS FOR DRAMS Last but not least Reliability Time to breakdown Ba0.47Sr0.53TiO3 at various OMR Time to breakdown Ba 0.47 Sr 0.53 TiO 3 Deposited on various electrodes TDDB for various DRAM dielectrics

28 HIGH-K DIELECTRICS FOR DRAMS High-k dielectrics (BST film ) has become the dielectric material of choice for cell capacitor of the dynamic random access memory devices (DRAMs) having gigabit densities To continue shrinking technology, BST thin films will be a productive field of research and development.

29 SUMMARY To continue Moore s law for next decades, New materials are needed. High-k dielectrics may ultimately lead to vaster and enable applications. Industry is seeking for new materials and technologies that can replace SiO2 and scaling remains continue.

30 References 1. H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A Brown, C.D. Young,P.M. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner, R.W. Murto High-k gate stacks for planar, scaled CMOS integrated circuits (2003). 2. Cheol Seong Hwang (Ba,Sr)TiO3 thin films for ultra large scale dynamic random access memory. A review on the process integration.(1998) 3. S. Ezhilvalavan, Tseung-Yuen Tseng Progress in the developments of (Ba,Sr)TiO3 (BST) thin films for Gigabit era DRAMs (2000). 4. G. D. Wilk, R. M. Wallaceb, J. M. Anthony High- kgate dielectrics: Current status and materials properties considerations (2001). 5. Ofer Sneh*, Robert B.Clark-Phelps, Ana R.Londer gan, Jereld Winkler, Thomas E.Seidel Thin film atomic layer deposition equipment for semiconductor processing (2002). 6. E.P. Gusev, E. Cartier, D.A. Buchanan, M. Gribelyuk, M. Copel, a H. Okorn-Schmidt, C. D Emic Ultrathin high-k metal oxides on silicon: processing, characterization and integration issues (2001).

31 References 7. D. E. Kotecki,J. D. Baniecki,H. Shen,R. B. Laibowitz,K. L. Saenger,J. J. Lian,T. M Shaw,S. D. Athavale,C. Cabral, Jr.,P. R. Duncombe,M. Gutsche,G. Kunkel,Y.- J. Park,Y.-Y. Wang,R. Wise (Ba,Sr)TiO3 dielectrics for future stacked capacitor DRAM (1999). 8.Intel s High Gate k/metal Gate Announcement November 4th, Wilman Tsai and Robert Chau Integration of Metal gate-high k Dielectrics to Extend Transistor Scaling (2004).