4 th Workshop on Innovative Memory Technologies

Transcription

1 Resistive RAM (ReRAM) Technology for High Density Memory Applications Sunjung Kim Semiconductor R&DC Center SAMSUNG Electronics 4 th Workshop on Innovative Memory Technologies

2 Contents Introduction NAND Scaling Technologies & Barriers Samsung Vertical ReRAM (VRRAM) VRRAM vs. 3D cross-point ALD/CVD ReRAM Properties VRRAM Integration & Challenges Selector-less Cell for VRRAM Review on Self-Rectifying Cell (SRC) Technologies Conclusions 2/ 33

3 Scaling Technology of NAND Flash Litho. Shrink : AFi ArF-imm. Double-PT Quadruple-PT # of cells increase : ? Vertical 3-D Stack Multi-Bit : bit? (data processing + ECC ) CG FG STI Air Gap Rule [nm] Design Multi bit Planar FG QPT /DPT 64cell NAND Physical DR 2xnm NAND Source : 2010 IEDM, page 98 & page 103 2D NAND era 3D NVM era Year 3/ 33

4 Scaling Barriers of NAND Flash Scaling Barriers seem difficult to be overcome from 10 nodes. WL-WL leakage : High PGM_V, Tun_Oxide (Etun.OX. ~ EWL) # of electron decrease : Cstorage (High-K) Bigger cell coupling : Thin storage, ECC 3D NVM [Parasitic capacitance coupling of FG] J. D. Lee, IEEE EDL, pp , / 33

5 Scaling Breakthrough with 3D Structures Planar > VNAND for sub-20nm > VRRAM for sub-10nm scaling TCAT (VNAND) VRRAM (Vertical ReRAM) ReRAM Cell J.H. Jang, Samsung, 2009 VLSI Tech., p I.G. Baek, Samsung, 2011 IEDM, p / 33

6 Contents Introduction NAND Scaling Challenges Samsung Vertical ReRAM (VRRAM) VRRAM vs. 3D cross-point ALD/CVD ReRAM Properties VRRAM Integration & Challenges Selector-less Cell for VRRAM Review on Self-Rectifying Cell (SRC) Technologies Conclusions 6/ 33

7 3D ReRAM Technology Traditional 3D x-point array vs. innovative VRRAM structure 7 / 33

8 Fabrication Cost of 3D X-point ReRAM Cost ~ # of Critical masks The # of stacks is limited by the affordable # of masks Cost effective # of stacks < 8 stacks (4 stacks with DPT) Cost ~ Lithography tools EUV must be used to reach > 512Gb even with 2bit MLC Only 2 more generations may be covered with 3D X-point ReRAM 3D X-point is only a temporary solution I.G. Baek, Samsung, 2011 IEDM, p Chip area x Cell efficiency = 100mm 2, 2bit MLC, 4F 2 unit cell assumed 8 / 33

9 Scalability of VRRAM Compared to 3D X-point, the # of critical masks relatively independent of the # of stacks. Compared to VNAND, ~ smaller cell area and ~ shorter stack height. V-NAND V-RRAM Poly channel CTF stack Electrode Switching material (direct tunneling limited > 5 nm) WL e e e e ee Short ch. effect Vertical coupling WL leakage WL WL Charge spreading WL J.D. Choi, Samsung, 2011 VLSI, p / 33

10 Process Requirements of VRRAM Cell material deposition with high step coverage High A/R dry etching Selective wet etching, treatment Good diffusion barrier, etch stopper materials Low heat budget 3D inspection methodology 10/ 33

11 Contents Introduction NAND Scaling Challenges Samsung Vertical ReRAM (VRRAM) VRRAM vs. 3D cross-point ALD/CVD ReRAM Properties VRRAM Integration & Challenges Selector-less Cell for VRRAM Review on Self-Rectifying Cell (SRC) Technologies Conclusions 11/ 33

12 Reference Planar ReRAM TMO : PVD Ta /ALDTa 2 O 5 ( ~ Ta 2 O 5-x ) Electrodes : PVD TiN (TE), CVD TiN (BEC) I_sw < 100uA, V_sw < 2.5V (pulse) t_sw ~ 10ns Endurance > 1E SET V G :2 V 10-4 RESET V G :3 V 0.2 V 10-5 Curre ent (A) Set Reset Drain Voltage (V) Curre ent (A) SET: 10ns/2.5V RESET: 10ns/-2.5V Cycles (N) 1 order of S/W window with >1E6 endurance I.G. Baek, Samsung, 2011 IEDM., p / 33

13 PVD-free Planar ReRAM TMO : ALD Ta 2 O 5 Electrodes : CVD TiN (TE, BEC) No memory switching : leaky Cl from CVD TiN TE enhances TiN/Ta 2 O 5 intermixingi i TaN, TaO generation at the interface 10-3 TOF-SIMS depth profiles of PVD TiN/ALD Ta 2 O 5, CVD TiN/ALD Ta 2 O (A) Current CVD TiN / ALD Ta 2 O Voltage (V) No S/W window, poor CVD TiN interface quality I.G. Baek, Samsung, 2011 IEDM., p / 33

14 S/W Properties with a Diffusion Barrier ALD based diffusion barrier with optimum thickness Cur rrent (A) CVD TiN B arrier + CVD TiN CVD TiN Barrier layer TaO x Voltage (V) Reference S/W properties are reproduced with only CVD and ALD processes I.G. Baek, Samsung, 2011 IEDM., p / 33

15 Current (A) Reliabilities with a Diffusion Barrier V SET: 10ns/2.5V B arrier + RESET: 10ns/-2.5V 25V CVD TiN Cycles (N) Time to fa ail (hr) o C 10 years 85 o C 180 o C 200 o C /T (1000/K) PVD (Ref.) B arrier + CVD TiN Endurance : > 1E6 Retention : ~ No critical reliability degradation was observed with CVD TiN + ALD barrier I.G. Baek, Samsung, 2011 IEDM., p / 33

16 Contents Introduction NAND Scaling Challenges Samsung Vertical ReRAM (VRRAM) VRRAM vs. 3D cross-point ALD/CVD ReRAM Properties VRRAM Integration & Challenges Selector-less Cell for VRRAM Review on Self-Rectifying Cell (SRC) Technologies Conclusions 16/ 33

17 Process Integration of VRRAM (1/2) Vertical NAND processes are mainly used except for the cell stack, vertical electrode and selection Tr. I.G. Baek, Samsung, 2011 IEDM., p / 33

18 Process Integration of VRRAM (2/2) VNAND (TCAT/BiCS) VRRAM Storage layer ONO TMO/Barrier Vertical Channel Poly-Si TiN (VE) Horizontal Line W / poly Si (W/L) W (HE) Selection Tr High V, Low I Low V, High I Process Temp. High (>700C) Low (<400C) I.G. Baek, Samsung, 2011 IEDM., p / 33

19 S/W Properties of VRRAM TMO : ALD Barrier / ALD Ta 2 O 5 Electrodes : CVD TiN (VE), CVD W/TiN (HE) I_sw < 80uA, V_sw < 4V t_sw < 1us (due to high parasitic RC) Endurance > 1e2 Curren nt (A) I reset : 80 μa C.C : 50μA VRRAM Voltage (V) Curren nt (A) R e 0.2 V SET: 1μsec/4V RESET: 1μsec/-5V 10-8 Cycles (N) First reported results using PVD-free process in a vertical structure I.G. Baek, Samsung, 2011 IEDM., p / 33

20 Challenges for VRRAM Demonstrated VRRAM using cost effective 3D process. But the major challenges for VRRAM include; Self-Rectifying Cell (SRC) SRC reduces leakage currents and cell-to-cell disturbance enables larger array size - Highly non-linear, asymmetric I-V characteristics are necessary High cell efficiency i Larger memory block with smaller overhead chip area - Low operation current needed - Layout optimization of driving circuits and vertical interconnection are necessary Developing SRC is most critical for VRRAM 20/ 33

21 Contents Introduction NAND Scaling Challenges Samsung Vertical ReRAM (VRRAM) VRRAM vs. 3D cross-point ALD/CVD ReRAM Properties VRRAM Integration & Challenges Selector-less Cell for VRRAM Review on Self-Rectifying Cell (SRC) Technologies Conclusions 21/ 33

22 Selector ½V read scheme and sneak current Need selector (function) to avoid sneak current 22/ 33

23 Why Selector-less (Self-Rectifying) Cell VRRAM Density H.S. Yoon, Samsung, VLSI Tech., 2009 Cross-point Process complexity Operation voltage X.A. Tran, IEDM / 33

24 ISSCC 2010, LETI Memory W/S 2011 Unity SRC Examples Current ratio 1000:1 Epitaxial i CMOx (ex. PrCaMnO) 24/ 33

25 IEDM 2010 GwangjuInst. Sci. Tech. (GIST) SRC Examples Back-to-back connection of HfO/ZrO stack Thick MIMIM stack 25/ 33

26 IEDM 2011 NanyangTech. Univ. (NTU) SRC Examples Simple n+si/hfox/ni stack Uni-polar switching 26/ 33

27 SRC Examples VLSI 2012 Macronix 0T1R CBRAM array SiO/HfO stack + Cu-GST layer 27/ 33

28 In Short... Targeting to what Unity presented in this W/S last year. But using fab-friendly materials (transition metal oxides) LETI Memory W/S 2011 Unity 28/ 33

29 Contents Introduction NAND Scaling Challenges Samsung Vertical ReRAM (VRRAM) VRRAM vs. 3D cross-point ALD/CVD ReRAM Properties VRRAM Integration & Challenges Selector-less Cell for VRRAM Review on Self-Rectifying Cell (SRC) Technologies Conclusions 29/ 33

30 Conclusions 1. Vertical ReRAM (VRRAM) has been successfully demonstrated as a cost effective post-nand solution. 2. Compared to the 3D X-point ReRAM, VRRAM has advantages when stacking >8 stacks with relaxed patterning technology. We expect VRRAM technology can be extensible beyond 1Tb era with ArF-i tools. 3. Self-rectifying cell technology would be main challenges for VRRAM production. 30/ 33

31 One Day... 31/ 33

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33 Acknowledgement In-Gyu Baek & Jungdal Choi Advanced Process Development Team Semiconductor R&D Center Samsung Electronics 33/ 33