# Design and Implementation of Delay Efficient Carry Select Adder Using D-Latch

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2 and 4) full carry generation (FCG). Suppose two n-bit operands are added in the conventional CSLA, then RCA- and RCA-2 generate n-bit sum (s and s) and output-carry (c out and c out ) corresponding to input-carry (c in= and c in = ), respectively. Logic expressions of RCA- and RCA-2 of the SCG unit of the n-bit CSLA are given as As shown in Fig. 2, the RCA calculates n-bit sum s and c out corresponding to c in =. The BEC unit receives s and c out from the RCA and generates (n + )-bit excess- code. The most significant bit (MSB) of BEC represents c out, in which n least significant bits (LSBs) represent s. The logic expressions s (i) = A(i) B(i) c (i) = A(i) B(i) (a) s (i) = s (i) c (i ) (b) c (i) = c (i) + s (i) c (i ) c out =c (n ) (c) s (i) = A(i) B(i) c (i) = A(i) B(i) (2a) s (i) = s (i) c (i ) (2b) c (i) = c (i) + s (i) c (i ) c out =c (n ) (2c) where c ( ) =, c ( ) =, and i n. As shown in (a) (c) and (2a) (2c), the logic expression of {s (i), c (i)} is identical to that of {s (i), c (i)}. These redundant logic operations can be removed to have an optimized design for RCA-2, in which the Half Sum Generation and Half Carry Generation of RCA- is shared to construct RCA-2. Based on this, [4] and [5] have used an add-one circuit instead of RCA-2 in the CSLA, in which a BEC circuit is used in [6] for the same purpose. Since the BEC- Fig. 2. Structure of the BEC-based CSLA; n is the input operand bit-width. of the RCA are the same as those given in (a) (c). The logic expressions of the BEC unit of the n- bit BEC-based CSLA are given as s () = s () c () = s () s (i) = s (i) c (i ) (3a) (3b) c (i) = s (i) c (i ) c out = c (n ) c (n ) (3c) (3d) for i n. We can find from (a) (c) and (3a) (3d) that, in the case of the BEC-based CSLA, c depends on s, which otherwise has no dependence on s in the case of the conventional CSLA. The BEC method therefore increases data dependence in the CSLA. We have considered logic expressions of the conventional CSLA and made a further study on the data dependence to find an optimized logic expression for the CSLA. Fig.. (a) Conventional CSLA; n is the input operand bitwidth. (b) The logic operations of the RCA is shown in split form, where HSG, HCG, FSG, and FCG represent half-sum generation, half-carry generation, full-sum generation, and full-carry generation, respectively. based CSLA offers the best area delay power efficiency among the existing CSLAs, we discuss here the logic expressions of the SCG unit of the BEC-based CSLA as well. III. CSLA USING D-LATCH LOGIC This method replaces the BEC circuit by D-latch. Latches are used to store -bit binary information. The latch is one of the sequential circuits so Their outputs are depends on the present inputs and previous inputs. In other words, the latch is level sensitive, so whenlatch are enabled, the operation of latch is changes according with input signal of the latch. The architecture of proposed 6-bit Carry Select Adder is shown in Fig. 3. In this we are using five different Page 2

4 directly given as an inputto the (:5) multiplexer without any delay. Now the (:5) multiplexer selectsthe sum bit according to the carry generated from (8:4) multiplexer which is theselection bit and the inputs of the (:5) multiplexer are the outputsobtained when en= and. The bits from a and b (i,e a[5:] and b[5:]) are given as inputs to (5:)RCA along with en as carry. When en=, the output of the(5:)rca is fed as input to the (5 bit) D-Latch and the output ofthe (5 bit) D-latch follows the input and given as an input tothe (2:6)multiplexer. When en=, the last state of the (5 bit) Dinput is trapped and held in the latch and thereforethe output from the (5:)RCA is directly given as an inputto the (2:6) multiplexer without any delay. Now the (2:6) multiplexer selectsthe sum bit according to the carry generated from (:5) multiplexer which is theselection bit and the inputs of the (2:6) multiplexer are the outputsobtained when en= and. Table : Results For The Selected Device XC3S6E-5FG32 V. RESULTS Graphical representation of Delay in 64-bit CSLA using D- Latch Fig 6: RTL Schematic view of 64 bit CSLA with D-Latch Fig 7: Waveform of 64 bit CSLA with D-Latch VI. CONCLUSION Addition is the most common and often used arithmetic operation on microprocessor, digital signal processor, especially digital computers. Also, it serves as a building block for synthesis all other arithmetic operations. Therefore, regarding the efficient implementation of an arithmetic logic unit, the adder structures become a very critical hardware unit. A D-LATCH based CSLA architecture is proposed in this project to reduce the delay of CSLA architecture than the recently proposed BEC based CSLA architecture. The functionality verification of the design is carried out by using ISE Simulator and the synthesis is also carried out by the XILINX ISE 2.3i.The HDL used for obtaining an RTL schematic and for designing the modules is VERILOG. From the graphs and the tables it is concluded that, the proposed D-LATCH based design is having less delay when compare to the BEC based and RCA based architectures. Page 4

5 Future Scope: With the increase in silicon densities, it is becoming feasible for compression systems to be implemented in a single chip. Here we have implemented CSLA using D-latch approach with less Delay. In future, we further reduce Area and Power parameters without the penalty of resources. REFERENCES [] B. Ramkumar and Harish M Kittur, Low Power and Area Efficient Carry Select Adder IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS-2. [2] Bedrij, O. J., (962), Carry-select adder, IRE Trans.Electron. Comput., pp [3] Ceiang,T. Y. and Hsiao,M. J.,(Oct. 998 ), Carry-select adder using single ripple carry adder, Electron. Lett., vol. 34, no.22, pp [4] Ramkumar,B.,Kittur, H.M. and Kannan,P. M.,(2 ), ASIC implementation of modified faster carry save adder, Eur. J. Sci.Res., vol. 42, no.,pp.53 58,2. [5] J.M.Rabaey, Digtal Integrated Circuits A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2. [6] E. Abu-Shama and M. Bayoumi, A New cell for low power adders, in Proc.Int. Midwest Symp. Circuits and Systems, 995,pp. 4 7 [7] Oklobdzija. V. G, High Speed VLSI Arithmetic Units: Adders and Multipliers, in Design of High Performance Microprocessor Circuits, Book edited by A.Chandrakasan, IEEE Press,2. Page 5

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