In-Rush Current Limit MOSFET Driver

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1 In-Rush Current Limit MOSFET Driver Si975 FEATURES 2.9- to 3-V Input Operating Range Microprocessor RESET Integrated High-Side Driver for N-Channel MOSFET Programmable di/dt Current DESCRIPTION The Si975 current limit MOSFET interface IC is designed to operate between a power source and a load using a low on-resistance power MOSFET with a sense terminal or in conjunction with a low ohmic sense resistor. The Si975 current limiter prevents source and load transients during hot swap and power-on with programmable dv/dt and di/dt. Both turn-on and steady-state current limits can be individually programmed, providing protection against short circuits. Power on RESET and logic controls allow complete microprocessor interfacing. The RESET function of the Si975 is industry-standard with full programmability. The Si975 is available in a 6-pin SOIC package and is rated over the commercial temperature range ( to 7 C). The Si975 is available in both standard and lead (Pb)-free packages. FUNCTIONAL BLOCK DIAGRAM R BIAS Bias Ref Boost COIL BOOST L BOOST HI/LO ENABLE Control Gate Drive POR GATE C BOOST Low R DS N-Channel FET STATUS C GATE I BIAS C RETRY Retry Delay Overcurrent + SENSE LIMSET R LIMSET R SENSE (mw) C RST GND POR Bandgap POR Reset Delay Ref Reset + Ref LOAD V RST RESET Load V LOAD Document Number: 728 S-4754 Rev. D, 9-Apr-4

2 Si975 ABSOLUTE MAXIMUM RATINGS Voltages Referenced to Ground V Boost Voltage V Inputs/Outputs (except Gate, Boost and V RST ) to +.3 V V RST Input Current ( < V RST < 5 V) ma Inputs/Outputs Current ma RESET Current ma STATUS Current ma Storage Temperature to 25 C Junction Temperature C Power Dissipation (package) a 6-Pin SOIC b mw Thermal Impedance ( JA ) C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mw/ C above 25 C. *. Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time SPECIFICATIONS Supply Parameter Symbol Test Conditions Unless Specified Limits 2.9 V 3.2 V to 7 C HI/LO = GND, R BIAS = 2.5 k L BOOST = H, C BOOST = nf Min a Typ b Max a Unit Quiescent Current I Q ENABLE =Logic Low 4 8 ma Logic Enable Turn-On Voltage V EN(on).3 x V Enable Turn-Off Voltage V EN(off).7 x Enable Source Current I ENSRC V ENABLE = V 4 2 A Turn-On Time t ON See Figure 3 Turn-Off Time t OFF Turn-On Boost t ON(BST) See Figure 4 6 s t OFF Initial Short Circuit t OFF(ISC) C GATE = 33 nf, See Figure 6 t OFF Short Circuit t OFF(SC) C GATE = 33 nf, See Figure 7 2 Status Output Voltage V STAT I SINK = 2 A.4 V Status Output Delay Time t STDLY See Figure 8 25 s Status Threshold V STATTHR.85 x.95 x HI/LO Turn-On Voltage V HILO(on).7 x V HI/LO Turn-Off Voltage V HILO(off).3 x Gate Drive Enhancement Voltage (V GATE V SENSE ) V GS V Source Current I SOURCE V CBOOST = 9 V Sink Current I SINK Current Sense Circuit Current Sense Amplifier Common Mode Range V CMR +.3 V Current Sense Amplifier Voltage Offset V OS 3 3 mv Current Sense Amplifier Bias Current I SOS Normal Operation.2 R LIMSET Reference Current I RLIMSET Current Sense Amplifier Hysteresis V HYST 2 Current Sense Amplifier Series Offset V SOS HI/LO =, V CMR >.5 V 2 Power On Reset RESET Output Voltage V OP(rst) I OUT = ma, > 2 V.4 V RESET Output Hysteresis c V HYST See Note c RESET Comparator Input Threshold V RST 5 5 ma A mv 2 mv V 2 Document Number: 728 S-4754 Rev. D, 9-Apr-4

3 Si975 SPECIFICATIONS Parameter Power On Reset Symbol Test Conditions Unless Specified 2.9 V 3.2 V HI/LO = GND, R BIAS = 2.5 k L BOOST = H, C BOOST = nf Min a Limits to 7 C RESET Comparator Offset Voltage d V RBIAS.5 mv RESET Comparator Input Bias Current I BIAS.2 A RESET Timer Delay t RSTD C RST = 5 nf, See Figure s RETRY t RETRY C RETRY = nf ms Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test. c. In a practical situation, V HYST is multiplied by ratio of a resistor divider chain. For = 3.2 V, V HYST = 2 mv. d. The RESET comparator input threshold specification (V RST ) includes thereset comparator offset voltage. Typ b Max a Unit PIN CONFIGURATION AND ORDERING INFORMATION SOIC-6 BOOST 6 COIL GATE LOAD GND C RST C RETRY ORDERING INFORMATION Part Number Temperature Range Package SENSE LIMSET HI/LO RESET STATUS V RST Si975CY Si975CY-T to 7 C SOIC-6 Si975CY-T E3 ENABLE 8 9 R BIAS Top View PIN DESCRIPTION Pin Number Function Description BOOST Output of on-chip Boost converter. A -nf capacitor should be connected between BOOST and GND 2 Positive supply pin. 3 GATE Connection to external power MOSFET gate. 4 LOAD Connection to positive supply side of LOAD. 5 SENSE Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard MOSFET may also be used in conjunction with a low ohmic value shunt resistor. 6 LIMSET Connects overcurrent limit set resistor R LIMSET to the reference input of overcurrent trip comparator. 7 HI/LO CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND for low Capacitive loads and to for high capacitive loads. 8 ENABLE CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high. A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator 9 R BIAS resistor R LIMSET and the GATE (on) charge current. See Functional Description for equations. V RST Input to voltage monitor comparator. STATUS Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than 9% of. 2 RESET Open drain NMOS output. This pin is driven low during power on reset or when V RST is lower than the internal.25-v reference. 3 C RETRY A capacitor connected from this pin to GND programs the retry timer. 4 C RST A capacitor connected from this pin to GND programs the reset timer. 5 GND Negative supply pin. 6 COIL Connection to Boost converter inductor. Document Number: 728 S-4754 Rev. D, 9-Apr-4 3

4 Si975 FUNCTIONAL DESCRIPTION The Si975 together with an n-channel MOSFET provides the following functions: If the HI/LO pin is tied low the current limit is 2% higher during turn-on than the steady state current limit point. limits di/dt current for hot insertion applications provides complete short circuit protection high-side drive allows n-channel MOSFET to be used, for lower power dissipation industry-standard microprocessor reset function logic control input and outputs I LOAD x R SENSE >.2 x I BIAS x R LIMSET (with pin HI/LO=Low) If a higher current limit is needed at start-up, the HI/LO pin can be tied high. The equation becomes: (2) Setting the Current Limit (SENSE, HI/LO pins, R LIMSET, R SENSE ) I LOAD x R SENSE >.2 x I BIAS x R LIMSET + I BIAS ( k + R HI ) (HI/LO = High) (3) The current limit point is determined by the voltage across R SENSE, the value of R LIMSET, and the bias current. The current limit circuit is shown in Figure Notice that any current limit can be set at turn-on using an optional resistor, R HI. The steady state current is set by the equation: Relaxation Mode Current Limit (C RETRY pin) I LOAD x R SENSE > I BIAS x R LIMSET () Due to the highly capacitive nature of some loads, the Si975 has an option to increase the current limit point to a much higher level at turn-on. In this case, turn-on is defined as V GATE < V. This function is implemented with the HI/LO pin. In an overload condition, the Si975 will go into a relaxation mode current limit operation that not only protects the source and load, but also reduces the power dissipated in the MOSFET. When an overload is detected, the circuit quickly turns off, then goes into a retry mode whereby the current is ramped up slowly. If the fault still exists, the current will ramp down again. This sequence will repeat indefinitely at a period defined by 6 x C RETRY until the fault is removed. Typically, capacitors in the range of nf to F can be used on C RETRY, but the period should be >5 ms. Si975 I BIAS Overcurrent + k, 2% SENSE HI/LO GATE LIMSET HI/LO R HI (Optional) R LIMSET R SENSE I LOAD VLOAD nf 4 FIGURE. Document Number: 728 S-4754 Rev. D, 9-Apr-4

5 Si975 FUNCTIONAL DESCRIPTION (CONT D) di/dt Limiting On Hot and Cold Insertion (GATE pin) The GATE pin provides a constant current source that is used to control the rate of rise of the gate of the MOSFET, and hence to control the di/dt of the load and source current. The equation that governs the gate current is: boost inductor should typically be H, <3.5, >8 ma dc, and the boost capacitor should be nf. Logic Control (STATUS, ENABLE, RESET, V RST and C RST pins) I SOURCE.25 V x 2.2 ma R BIAS (for R BIAS = 2.5 k ) Typically, a 33-nF capacitor should be connected from the GATE pin to ground. If a large I SOURCE is needed for high di/dt, a 33- resistor in series with C GATE may be necessary to prevent oscillation. In the case that > 6 V, a resistor of approximately 33 is also recommended in series with the gate. (Figure ) Reference Bias Current (R BIAS pin) This pin sets the internal current used by R LIMSET to determine all the current limit points. Typically R BIAS = 2.5 k which sets a 2- A bias current. The equation which relates R BIAS to I BIAS is: (4) STATUS. The status monitor detects when the load voltage is 9% of input voltage, V LOAD >.9 x. This pin is an open-drain NMOS output, capable of sinking 2 A at V OL =.4 V. If this pin is used in conjunction with the ENABLE of another unit, power supply sequencing (or daisy-chaining) is easily implemented. ENABLE. This CMOS logic compatible input serves as the on/off control pin. This pin has 4- A minimum pull-up to. RESET (V RST, C RST, RESET pins). This is a standard implementation of the microprocessor reset function. A comparator looks at the voltage on V RST pin and compares it with.25 V. This function is programmable by using an external voltage divider. When V RST is higher than.25 V, the reset signal is delayed by the C RST pin, defined by Equation (6) and then goes high. (Figure 2) (5) Reset delay t RSTD 4 x C RST (6) I BIAS.25 V 2 A 5xR BIAS (for R BIAS = 2.5 k ) Power on Reset (POR) ( pin) HI/LO Pin R LIMSET C RETRY This function monitors the voltage on the pin and signals the system if all input voltage requirements have been met. At turn-on when > 2.7 V 2 mv, a POR signal is generated for a duration of s. After this point the system is released into operation. If falls below 2.7 V 2 mv, a second POR signal will be generated. If two POR signals are detected, this indicates that the source for is not capable of supplying the load current. The IC then turns off the MOSFET and initiates its retry period, hence fully protecting the MOSFET from an over-power condition. Current Turn-On V GATE > V Short Circuit Applied to Output Current Limit Point I LOAD Boost Converter (COIL, BOOST pins) The boost converter generates the gate drive for the external n-channel MOSFET. This is limited to typically + V. The Document Number: 728 S-4754 Rev. D, 9-Apr-4 FIGURE 2. Typical Operation Under Start-up Condition With An Overcurrent Fault Applied to the Output 5

6 Si975 TYPICAL CHARACTERISTICS (25 C UNLESS OTHERWISE NOTED) 3.5 Gate-Source Drive Current vs. R BIAS 3. Gate-Sink vs. Gate-Source Current (ma) I SOURCE I SINK Gate-Sink Current (ma) R BIAS (k ) (V) 5 R LIMSET Current vs. R BIAS 4 RESET Timer Delay vs. C RESET I R(LIMSET) R LIMSET Current ( A) t RSTD RESET Timer Delay ( S) R BIAS (k ) C RST (nf) 6 RETRY Delay vs. C RETRY 5 t RETRY RETRY Delay (ms) C RETRY (nf) 6 Document Number: 728 S-4754 Rev. D, 9-Apr-4

7 Si975 SWITCHING TIME TEST CIRCUITS ENABLE.7.3 t ON t OFF I SOURCE 5 % 5 % I SINK ENABLE I SOURCE t ON(bst) 5 % FIGURE 3. Normal-Mode Operation V BOOST t BOOST 9 % FIGURE 4. Timing Definition with ENABLE Already On FIGURE 5. Start of Boost Converter t RETRY I LOAD I LOAD V SENSE Threshold V SENSE Threshold t OFF(isc) t OFF(sc) V G V I SOURCE I SINK 5% FIGURE 6. First Short Circuit FIGURE 7. Relaxation-Mode Current Limit V G V LOAD Status Threshold STATUS t STDLY t STDLY.3 x RESET(2) t RSTD (2) With reset input divider correctly set, monitoring V LOAD FIGURE 8. STATUS and RESET Document Number: 728 S-4754 Rev. D, 9-Apr-4 7

8 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 9 Revision: 8-Jul-8

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