Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks

Transcription

1 Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks Cheoljoo Jeong Steven M. Nowick Department of Computer Science Columbia University

2 Outline Introduction Background Technology mapping Robust asynchronous threshold networks (NCL) NCL CAD flow Hazard issues: Orphans Motivational Examples Robustness & asynchronous technology mapping Robust Technology Mapping and Cell Merger Algorithms Experimental Results Near-complete DES encryption circuit ConcludingRemarks

3 Problem Definition Asynchronous Threshold Networks Robust asynchronous circuit that consists of threshold gates. Thresholdgates: Each input has a weight Fires when the weighted sum of inputs exceeds a threshold value. Cell Merger and Technology Mapping Problems Given: unoptimized robust netlist Produce: optimized robust netlist (consisting of library cells) Cell Merger Technology Mapping Input Unoptimized threshold network: robust Async technology library (characterized) Output Optimized cell-merged network: consists of library cells, preserves robustness Optimized mapped network: consists of library cells, preserves robustness

4 Related Work Technology Mapping for Asynchronous Circuits Siegel et al.: tech map for Burst-mode circuits Cortadella et al.: tech map for QDI control circuits Optimization of Asynchronous Threshold Circuits Smith et al.: a few local optimization techniques Theseus Logic: local cell merger P. Siegel et al. Automatic technology mapping for generalized fundamental-mode asynchronous designs. DAC Cortadella et al. Decomposition and technology mapping of speed-independent circuits. IEEE TCAD Smith et al. Optimization of NULL convention self-timed circuits. Integration

5 Summary of Results A robust technology mapping algorithm for asynchronous threshold networks is presented: First systematic approach to robust technology mapping Maps across both datapath and control circuits Maps sequential gates with hysteresis Targets either delay or area Integrates into existing asynchronous tool flow of Theseus Logic The cell merger problem formulated and solved: Limited special case of technology mapping Only adjacent cells in the given unoptimzed netlist can be merged Experimental Results: tech map Average output delay improvements: 2.9% Worst-case circuit delay improvements: 26.3% Average area improvements: 2.7%

7 Technology Mapping Technology Mapping Task of transforming an technology-independent network into a bound network as an interconnection of library elements [Step 1] Decomposition [Step 2] Partitioning [DeMicheli94] G. De Micheli. Synthesis and Optimization of Digital Circuits (1994).

8 Technology Mapping (cont.) (after decomposition and partitioning; from prev. slide) [Step 3] Covering Subject graph matches to library cells Mapped circuit

9 Overview of Null Convention Logic NCL (Null Convention Logic) Robust asynchronous design style based on threshold networks Uses delay-insensitive encoding Uses four-phase signaling protocol: alternates evaluate and reset phases Asynchronous threshold gates with hysteresis property Industrial applications by Theseus Logic

10 NCL Asynchronous Commercial CAD Flow (Theseus Logic) VHDL specification uses synchronous Synopsys tool: front-end 3NCL circuit abstract multi-valued circuit dual-rail expansion 2NCL circuit instantiated Boolean circuit (robust, unoptimized) Theseus s template-based cell merger Robust NCL circuit only limited local optimizations currently used

11 Basics of NCL Circuits 3NCL Circuits: Abstract multi-valued threshold circuit Starting point for NCL synthesis flow 3NCL is a three-valued with {, 1, NULL} 3NCL circuits alternate between DATA and NULL phases During the DATA (Evaluate) phase: outputs have DATA values only after all inputs have DATA values During the NULL (Reset) phase: outputs have NULL values only after all inputs have NULL values. 3-valued inputs a b 3NCL OR gate z 3-valued output

12 Basics of NCL Circuits 3NCL Circuits: Abstract multi-valued threshold circuit Starting point for NCL synthesis flow 3NCL is a three-valued with {, 1, NULL} 3NCL circuits alternate between DATA and NULL phases During the DATA (Evaluate) phase: outputs have DATA values only after all inputs have DATA values During the NULL (Reset) phase: outputs have NULL values only after all inputs have NULL values. 3-valued inputs a b N N N z 3-valued output 3NCL OR gate

13 Basics of NCL Circuits 3NCL Circuits: Abstract multi-valued threshold circuit Starting point for NCL synthesis flow 3NCL is a three-valued with {, 1, NULL} 3NCL circuits alternate between DATA and NULL phases During the DATA (Evaluate) phase: outputs have DATA values only after all inputs have DATA values During the NULL (Reset) phase: outputs have NULL values only after all inputs have NULL values. 3-valued inputs a b 1 N N z 3-valued output 3NCL OR gate

14 Basics of NCL Circuits 3NCL Circuits: Abstract multi-valued threshold circuit Starting point for NCL synthesis flow 3NCL is a three-valued with {, 1, NULL} 3NCL circuits alternate between DATA and NULL phases During the DATA (Evaluate) phase: outputs have DATA values only after all inputs have DATA values During the NULL (Reset) phase: outputs have NULL values only after all inputs have NULL values. 3-valued inputs a b 1 1 z 3-valued output 3NCL OR gate

15 Basics of NCL Circuits 3NCL Circuits: Abstract multi-valued threshold circuit Starting point for NCL synthesis flow 3NCL is a three-valued with {, 1, NULL} 3NCL circuits alternate between DATA and NULL phases During the DATA (Evaluate) phase: outputs have DATA values only after all inputs have DATA values During the NULL (Reset) phase: outputs have NULL values only after all inputs have NULL values. 3-valued inputs a b N 1 z 3-valued output 3NCL OR gate

16 Basics of NCL Circuits 3NCL Circuits: Abstract multi-valued threshold circuit Starting point for NCL synthesis flow 3NCL is a three-valued with {, 1, NULL} 3NCL circuits alternate between DATA and NULL phases During the DATA (Evaluate) phase: outputs have DATA values only after all inputs have DATA values During the NULL (Reset) phase: outputs have NULL values only after all inputs have NULL values. 3-valued inputs a b N N N z 3-valued output 3NCL OR gate

17 Basics of NCL Circuits (cont.) Delay-Insensitive Encoding Single signal is represented by two wires (-rail and 1-rail) a dual-rail expansion a a 1 a 1 a a NULL Not allowed - Motivation: robust data communication

18 Basics of NCL Circuits (cont.) Transforming 3NCL to 2NCL Circuits 2NCL circuits = dual-rail implementation of 3NCL circuits Single 3NCL signal: is represented by two wires (-rail / 1-rail) Single 3NCL gate: expanded into small network of 2NCL gates 3-valued inputs 3-valued output dual-rail inputs dual-rail output a b z a b z z 1 a 1 b 1 3NCL OR gate 2NCL OR network

19 Basics of NCL Circuits (cont.) Structure of NCL Circuits: Single Pipeline Stage Asynchronous registration Asynchronous registration Completion detector Stage N-1 Stage N Stage N+1

20 Basics of NCL Circuits (cont.) Pipeline Operation: Four-Phase Signaling Protocol Stages alternate between DATA (Evaluate) and NULL (Reset) phases CD CD Async Register Async Register Stage N-1 Stage N Stage N+1

21 Basics of NCL Circuits (cont.) Pipeline Operation: Four-Phase Signaling Protocol Stages alternate between DATA (Evaluate) and NULL (Reset) phases CD CD Async Register Async Register Stage N-1 Stage N Stage N+1 DATA (Evaluate) phase

25 Basics of NCL Circuits (cont.) Pipeline Operation: Four-Phase Signaling Protocol Stages alternate between DATA (Evaluate) and NULL (Reset) phases CD CD Async Register Async Register 1 Stage N-1 Stage N Stage N+1 DATA (Evaluate) phase

27 Basics of NCL Circuits (cont.) Pipeline Operation: Four-Phase Signaling Protocol Stages alternate between DATA (Evaluate) and NULL (Reset) phases CD CD Async Register Async Register Stage N-1 Stage N Stage N+1 NULL (Reset) phase

31 Basics of NCL Circuits (cont.) Pipeline Operation: Four-Phase Signaling Protocol Stages alternate between DATA (Evaluate) and NULL (Reset) phases 1 Async Register CD Async Register CD Stage N-1 Stage N Stage N+1 NULL (Reset) phase

32 Basics of NCL Circuits (cont.) Pipeline Operation: Four-Phase Signaling Protocol Stages alternate between DATA (Evaluate) and NULL (Reset) phases 1 1 Async Register CD Async Register 1 CD Stage N-1 Stage N Stage N+1 NULL (Reset) phase

33 Industrial Applications of Null Convention Logic Theseus Logic, Inc.: asynchronous startup company Built asynchronous version of Motorola MCORE processor 18+ other chips designed and fabricated using NCL flow Five had over 15, transistors Largest one 66, transistors. Currently, NCL used in DARPA CLASS project (led by Boeing) Major new CAD initiative (with Philips, Theseus, Columbia, UNC, etc.) Developing commercially-viable asynchronous CAD flow Our proposed tech map/cell merger methods to be included in flow

34 Hazard Issues Delay-Insensitivity (= Delay Model) Assumes arbitrary gate and wire delay circuit operates correctly under all conditions Most robust design style Orphans : Hazards to Delay-Insensitivity Ineffective signal transition sequences (= unobservable paths) Wire orphans: timing requirements on wires at fanout points Gate orphans: timing requirements on paths at fanout points

35 Hazard Issues (cont.) Wire Orphan Example: primary outputs Wire orphan example In NCL flow, wire orphans are not a problem: eliminated by enforcing physical timing constraints

38 Hazard Issues (cont.) Wire Orphan Example: primary outputs wire orphan! Wire orphan example In NCL flow, wire orphans are not a problem: eliminated by enforcing physical timing constraints

39 Gate Orphan Example: Hazard Issues (cont.) a b z z 1 a 1 b 1 Gate orphan example In NCL flow, gate orphan freedom not guaranteed: must be avoided during synthesis

42 Gate Orphan Example: Hazard Issues (cont.) gate orphan! = not observable a b z z 1 a 1 b 1 Gate orphan example In NCL flow, gate orphan freedom not guaranteed: must be avoided during synthesis

44 Motivational Examples: Challenges to Robust Technology Mapping Arbitrary decomposition can be dangerous (= non-robust). a b c 3-input AND gate a b c decomposition into two 2-input AND gates CONCLUSION: must carefully restrict decomposition to ensure robustness

45 Motivational Examples: Challenges to Robust Technology Mapping Arbitrary decomposition can be dangerous (= non-robust). gate orphan! a b c 3-input AND gate a b c decomposition into two 2-input AND gates CONCLUSION: must carefully restrict decomposition to ensure robustness

46 Motivational Examples : Challenges to Robust Technology Mapping DAG (Directed Acyclic Graph)-based covering can be dangerous. a z a b c d z w b c d w subject graph = DAG mapped network CONCLUSION: must avoid arbitrary DAG-covering for robustness

48 Cell Merger Algorithm The Cell Merger Problem Input: unoptimized robust netlist Output: optimized robust netlist (consists of library cells) Solved as limited special case of technology mapping Only adjacent cells in the given unoptimized netlist can be merged Overview of the Proposed Algorithm No decomposition (NEW) Every cell function is a base function Original netlist is subject graph Partitioning (use existing techniques) Pattern graph generation (NEW) New bottom-up approach proposed Matching and covering (use existing techniques)

49 Pattern Graph Generation Overview of Pattern Graph Generation Iteratively generates all pattern graphs in single bottom-up approach Generates: two-cell merger, three-cell merger (up to four-cell mergers) Includes all single-cell pattern graphs: may be useful for matching Merges cell functions rather than cells themselves Single cell function may represent multiple cells Examples: Two-cell merger: merging AND2 and OR2 Three-cell merger: merging AND2 and OR2

50 Matching and Covering Matching and Covering Uses traditional synchronous approach (with dynamic programming) Targets either area or delay minimization Delay Minimization Nonlinear delay model used matches to library cells based on table-lookup uses load binning to handle load-dependent delays alternative approach: use load-independent delay model

51 Technology Mapping Algorithm The Technology Mapping Problem Input: unoptimized robust netlist Output: optimized robust netlist (consists of library cells) More general approach Allows more general mapping to library cells Overview of the Proposed Algorithm Gate-orphan-free decomposition (NEW) Decompose original netlist into gate-orphan-free netlist Partitioning (use existing techniques) Pattern graph generation (NEW) Use new positive monotonic finite basis (= AND2/OR2) vs. synchronous approaches (= NAND2/INV) Must include some complex irreducible nodes Matching and covering (use existing techniques)

52 Gate-Orphan-Free Decomposition Basic Idea Decompose each node using simple base functions new monotonic basis proposed = AND2/OR2 safe as long as no gate orphans introduced If no such guarantee: node not decomposed: the node function is registered as new complex base function (irreducible) Overview of Gate-Orphan-Free Decomposition AND2 and OR2 gates: not decomposed = primitive base functions Large OR cells: safely decomposed into network of OR2 cells Large AND cells: not decomposed -- decomposition unsafe Existing (Theseus) local cell merger optimizations undone through reverse lookup table Otherwise, do not decompose nodes -- decomposition unsafe

53 Pattern Graph Generation After decomposition and partitioning, subject graphs consist of: simple base functions (AND2/OR2) complex base functions (irreducible) Overview of Pattern Graph Generation: Library cell functions: decomposed using simple finite basis. If library cell function = complex base function, then: special pattern graph is added = single irreducible node

54 Matching and Covering Matching and Covering Uses traditional synchronous approach (with dynamic programming) Targets either area or delay minimization Delay Minimization Nonlinear delay model used matches to library cells based on table-lookup uses load binning to handle load-dependent delays alternative approach: use load-independent delay model

56 Experimental Results (cont.) Results for Cell Merger Area-optimized circuit Delay-optimized circuit Name #i/#o/#g Area Delay Area Delay des-r1 352/64/179 1.% 1.2% 11.9% 87.4% des-r2 11/4/1 95.7% 95.3% 1.% 73.8% des-r3 59/298/ % 1.% 14.1% 83.5% des-r4 59/36/ % 1.% 12.1% 83.6% des-r5 3/2/4 75.3% 8.5% 83.4% 57.5% Average improvement 99.9% 99.9% 13.2% 83.7%

57 Experimental Results Results for Technology Mapping Area-optimized circuit Delay-optimized circuit Name #i/#o/#g Area Delay Area Delay des-r1 352/64/ % 1.2% 11.7% 73.3% des-r2 11/4/1 95.7% 95.3% 155.9% 71.% des-r3 59/298/ % 1.3% 122.6% 79.7% des-r4 59/36/ % 1.3% 122.3% 8.% des-r5 3/2/4 75.% 8.5% 83.3% 57.5% Average improvement 97.3% 1.2% 12.4% 79.1%

58 Experimental Results (cont.) Delay Optimization Avg. improvement for worst-case output delay Considers single worst-case path for each individual output Cell Merger: 16.3% Tech map:2.9% Avg. improvement for worst-case circuit delay Considers the single worst-case path in entire circuit Cell Merger: 2.1% Tech map:26.3% Area Optimization Cell Merger:.1% avg. improvement Tech map: 2.7% avg. improvement Analysis of results Due to its local nature, Theseus optimizer left more room for improvement w.r.t. delay than w.r.t. area

59 Concluding Remarks Conclusions Robust technology mapping and cell merger algorithms for asynchronous threshold circuits proposed Fully-automated in software tool Avg. improvements for tech map Delay: 2.9% Area: 2.7% Worst-case circuit paths: delay improvements of 26.3% Our method to be included in DARPA CLASS async tool flow Future Work Careful robust extension of DAG-covering algorithms Support hybrid cost functions (e.g. area and delay) Robust multi-level optimization of asynchronous threshold networks

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61 Asynchronous Circuits Synchronous vs. Asynchronous Systems Synchronous System global clock entire system operates at fixed rate centralized control Asynchronous System no global clock components operate at varying rates distributed control (communicate locally via handshaking) clock handshaking interfaces Synchronous System Asynchronous System

62 Asynchronous Circuits (cont.) Industrial Applications of Asynchronous Circuits Sun: UltraSPARC uses async FIFOs for memory interface Theseus Logic: asynchronous Motorola MCORE processor Philips: Feb. 26 press release: asynchronous ARM processor commercially available by ARM Ltd. Sold tens of millions of async pager chips and smart cards

63 Basics of NCL Circuits (cont.) Asynchronous Threshold Gates with Hysteresis Property Threshold gates with sequential SET/RESET functionality SET function: Each input x i has weight w i Gate has threshold value T If weighted sum Σw i x i >= T, gate fires RESET function: The gates reset only after all inputs change to s.

64 Asynchronous Circuits Benefits of Asynchronous Circuits Robustness to process variation Mitigates: timing closure problem Low power consumption, low EMI Modularity Challenges of Asynchronous Circuits Lack of CAD tools Robust design is required: hazard-freedom Area overhead