ASYNCHRONOUS PULSE LOGIC

Transcription

1 List of Figures Preface Acknowledgments First Author s Personal Thanks xi xv xxi xxiii 1. PRELIMINARIES 1 1 High-speed CMOS-circuits 1 2 Asynchronous protocols and delay-insensitive codes 3 3 Production rules 4 4 The MiniMIPS processor 4 5 Commonly used abbreviations 6 2. ASYNCHRONOUS PULSE-LOGIC BASICS 7 1 Road map of this chapter 9 2 The pulse repeater Timing constraints in the pulse repeater Simulating the pulse repeater The synchronous digital model Asymmetric pulse-repeaters 20 3 Formal model of pulse repeater Basic definitions Handling the practical simulations Expanding the model Using the extended model Noise margins 28 4 Differential-equations treatment of pulse repeater Input behavior of pulse repeater 30

2 vi ASYNCHRONOUS PULSE LOGIC 4.2 Generalizations and restrictions COMPUTING WITH PULSES 37 1 A simple logic example 38 2 Pulse-handshake duty-cycle 42 3 Single-track handshake interfaces 45 4 Timing constraints and timing assumptions 46 5 Minimum cycle transition-counts 47 6 Solutions to transition-count problem 48 7 The APL design-style in short A SINGLE-TRACK ASYNCHRONOUS PULSE- LOGIC FAMILY: I. BASIC CIRCUITS 51 1 Preliminaries Transition counting in pipelined asynchronous circuits Transition-count choices in pulsed circuits Execution model Capabilities of the STAPL family Design philosophy 58 2 The basic template Bit generator Bit bucket Left-right buffer 66 3 Summary of properties of the simple circuits A SINGLE-TRACK ASYNCHRONOUS PULSE- LOGIC FAMILY: II. ADVANCED CIRCUITS 73 1 Multiple input and output channels Naïve implementation Double triggering of logic block in the naïve design Solution Timing assumptions 77 2 General logic computations Inputs whose values are not used 78 3 Conditional communications The same program can be expressed in several ways Simple techniques for sends General techniques for conditional communications 84 4 Storing state 89

3 vii 4.1 The general state-storing problem Implementing state variables Compiling the state bit 92 5 Special circuits Arbitration Four-phase converters 99 6 Resetting STAPL circuits Previously used resetting schemes An example Generating initial tokens How our circuits relate to the design philosophy Noise External noise-sources Charge sharing Crosstalk Design inaccuracies AUTOMATIC GENERATION OF ASYNCHRONOUS PULSE-LOGIC CIRCUITS Straightforwardly compiling from a higher-level specification An alternative compilation method What we compile The PL1 language Channels or shared variables? Simple description of the PL1 language An example: the replicator Compiling PL PL1-compiler front-end Determinism conditions Data encoding PL1-compiler back-end Slack Logic simplification Code generation A DESIGN EXAMPLE: THE SPAM MICROPROCESSOR The SPAM architecture SPAM implementation 134

4 viii ASYNCHRONOUS PULSE LOGIC 2.1 Decomposition 2.2 Arbitrated branch-delay 2.3 Byte skewing 3 Design examples 3.1 The PCUNIT 3.2 The REGFILE 4 Performance measurements on the SPAM implementation 4.1 Straightline program 4.2 Computing Fibonacci numbers 4.3 Energy measurements 4.4 Summary of SPAM implementation s performance 4.5 Comparison with QDI 8. RELATED WORK 1 Theory 2 STAPL circuit family 3 PL1 language 4 SPAM microprocessor 9. LESSONS LEARNED 1 Conclusion Appendices PL1 Report 0.1 Scope 0.2 Structure of PL1 1 Syntax elements 1.1 Keywords 1.2 Comments 1.3 Numericals 1.4 Identifiers 1.5 Reserved special operators 1.6 Expression operators 1.7 Expression syntax 1.8 Actions 2 PL1 process description 2.1 Declarations 2.2 Communication statement 2.3 Process communication-block

5 ix 3 Semantics Expression semantics Action semantics Execution semantics Invariants Semantics in terms of CHP Slack elasticity Examples 184 SPAM Processor Architecture Definition SPAM overview SPAM instruction format SPAM instruction semantics Operand generation Operation definitions Assembly-language conventions The SPAM assembly format 191 Proof that Definition 2.2 Defines a Partial Order Remark on Continuity 194