Digital Electronics Student Objectives One Credit

Similar documents
Digital Electronics Detailed Outline

Upon completion of unit 1.1, students will be able to

The components. E3: Digital electronics. Goals:

Gates, Circuits, and Boolean Algebra

Electronics Technology

1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

Lecture 8: Synchronous Digital Systems

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

A Digital Timer Implementation using 7 Segment Displays

Content Map For Career & Technology

Counters and Decoders

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks

Unit/Standard Number. High School Graduation Years 2010, 2011 and 2012

Principles of Engineering (PLTW)

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Operating Manual Ver.1.1

ELEC EXPERIMENT 1 Basic Digital Logic Circuits

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

University of St. Thomas ENGR Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54

Electronics Technology

CHAPTER 3 Boolean Algebra and Digital Logic

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

ANALOG & DIGITAL ELECTRONICS

Chapter 2 Logic Gates and Introduction to Computer Architecture

ESYST Residential Wiring

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

DEPARTMENT OF INFORMATION TECHNLOGY

T146 Electro Mechanical Engineering Technician MTCU Code Program Learning Outcomes

Course: Bachelor of Science (B. Sc.) 1 st year. Subject: Electronic Equipment Maintenance. Scheme of Examination for Semester 1 & 2

Module 3: Floyd, Digital Fundamental

Digital Fundamentals. Lab 8 Asynchronous Counter Applications

ENGI 241 Experiment 5 Basic Logic Gates

Copyright Peter R. Rony All rights reserved.

DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING

Test Code: 8094 / Version 1

List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).

Figure 8-1 Four Possible Results of Adding Two Bits

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design

Study Guide for the Electronics Technician Pre-Employment Examination

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

Seven-Segment LED Displays

BINARY CODED DECIMAL: B.C.D.

EXPERIMENT 8. Flip-Flops and Sequential Circuits

Digital Logic Elements, Clock, and Memory Elements

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell

Design and Development of Virtual Instrument (VI) Modules for an Introductory Digital Logic Course

Digital Logic Design Sequential circuits

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

Chapter 9 Latches, Flip-Flops, and Timers

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

ELECTRICAL/ELECTRONICS ENGINEERING TECHNOLOGY (EET) BODY OF KNOWLEDGE

Lesson 12 Sequential Circuits: Flip-Flops

ASYNCHRONOUS COUNTERS

Lab 1: Study of Gates & Flip-flops

Digital circuits make up all computers and computer systems. The operation of digital circuits is based on

ECEN 1400, Introduction to Analog and Digital Electronics

Binary Adders: Half Adders and Full Adders

COMBINATIONAL CIRCUITS

FORDHAM UNIVERSITY CISC Dept. of Computer and Info. Science Spring, Lab 2. The Full-Adder

EE360: Digital Design I Course Syllabus

Contents COUNTER. Unit III- Counters

PLL frequency synthesizer

Counters. Present State Next State A B A B

CHAPTER 11: Flip Flops

Active Learning in the Introduction to Digital Logic Design Laboratory Course

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

CMOS Binary Full Adder

Lecture-3 MEMORY: Development of Memory:

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

Course Requirements & Evaluation Methods

Apprentice Telecommunications Technician Test (CTT) Study Guide

Experiment teaching of digital electronic technology using Multisim 12.0

Digital Systems. Syllabus 8/18/2010 1

Flip-Flops, Registers, Counters, and a Simple Processor

(1) /30 (2) /30 (3) /40 TOTAL /100

RUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY

Decimal Number (base 10) Binary Number (base 2)

Counters & Shift Registers Chapter 8 of R.P Jain

3-Digit Counter and Display

CONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii

DATA SHEETS DE COMPONENTES DA FAMÍLIA LÓGICA TTL GATES AND INVERTERS POSITIVES NAND GATES AND INVERTERS DESCRIÇÃO

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

COURSE SYLLABUS. PRE-REQUISITES: Take CETT-1303(41052); Minimum grade C, CR.

Machine Architecture and Number Systems. Major Computer Components. Schematic Diagram of a Computer. The CPU. The Bus. Main Memory.

PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1

Combinational Logic Design Process

Yrd. Doç. Dr. Aytaç Gören

CHAPTER 11 LATCHES AND FLIP-FLOPS

Wiki Lab Book. This week is practice for wiki usage during the project.

AUTOMATIC NIGHT LAMP WITH MORNING ALARM USING MICROPROCESSOR

LOGICOS SERIE Precios sujetos a variación. Ref. Part # Descripción Precio Foto Ref. Quad 2-Input NOR Buffered B Series Gate / PDIP-14

WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

Karaoke Circuit Building Instructions

SEM 1 SEM 2 SEM 3 SEM 4 AMT BAHASA MELAYU I - IV

1. Oscilloscope is basically a graph-displaying device-it draws a graph of an electrical signal.

Transcription:

First Six Weeks DE 1.1(A) The student will know and practice proper safety while working with electronics. DE 1.1(B) The student will be able to express numbers in scientific notation, engineering notation, and System International (SI) notation. DE 1.1(C) The student will identify many of the common components used in electronics. DE 1.1(D) The student will be able to determine a resistor s nominal value by reading its color code. DE 1.1(E) The student will be able to determine a resistor s actual value by reading its resistance with a Digital Multimeter (DMM). DE 1.1(F) The student will be able to determine a capacitor s nominal value by reading its labeled nomenclature. DE 1.1(G) The student will be able to properly tin the tip of a soldering iron. DE 1.2(A) The student will be able to identify the parts of an atom and determine if an element would make a good conductor, insulator, or semiconductor. DE 1.2(B) The student will use Ohm s Law, Kirchhoff s Voltage Law, and Kirchhoff s Current Law to solve for simple series and parallel circuit. DE 1.2(C) The student will be able to use a Circuit Design Software to analyze simple analog circuits. DE 1.2(D) The student will be able to use a breadboard and digital multimeter to analyze simple analog circuits. DE 1.2(E) The student will be able to determine the amplitude, period, frequency, and duty cycle analog and digital signals. DE 1.2(F) The student will be able to analyze and design simple digital oscillators using the 555 Timer chip. DE 1.2(G) The student will utilize the Circuit Design Software (CDS) to simulate and test a complete analog design. DE 1.3(A) The student will be able to obtain and extract information from the manufacturer datasheets for components commonly used in digital electronics. DE 1.3(B) The student will know how to identify commonly used electronic components given their part number or schematic symbol. DE 1.3(C) The student will be able to identify various integrated circuit (IC) package styles. DE 1.3(D) The student will know the fundamental differences between combinational and sequential logic. DE 1.3(E) The student will identify and describe the function of AND, 10 Days 12 Days

OR, & Inverter gates. DE 1.3(F) The student will be able to use Circuit Design Software (CDS) to simulate and test a simple combinational logic circuit designed with AND, OR, & Inverter gates. DE 1.3(G) The student will identify and describe the function of a D flip-flop. Second Six Weeks DE 1.3(H) The student will be able to use Circuit Design Software (CDS) to simulate and test a simple sequential logic circuit design with D flip-flops. DE 1.3(I) The student will utilize the Circuit Design Software (CDS) to simulate and test a complete design containing both combinational and sequential logic. DE 2.1(A) The student will convert numbers between the binary and decimal number systems. DE 2.1(B) The student will translate design specifications into truth tables. DE 2.1(C) The student will extract un-simplified logic expressions from truth tables. DE 2.1(D) The student will construct truth tables from logic expressions. DE 2.1(E) The student will use the rules and laws of Boolean algebra, including DeMorgan s, to simplify logic expressions. DE 2.1(F) The student will analyze AOI (AND/OR/Invert) combinational logic circuits to determine their equivalent logic expressions and truth tables. DE 2.1(G) The student will design combinational logic circuits using AOI logic gates. DE 2.1(H) The student will translate a set of design specifications into a functional AOI combinational logic circuit following a formal design process. DE 2.1(I) The student will use Circuit Design Software (CDS) and a Digital Logic Board (DLB) to simulate and prototype AOI logic circuits. DE 2.2(A) The student will use the K-Mapping technique to simplify combinational logic problems containing two, three, and four variables. DE 2.2(B) The student will be able to solve K-Maps that contain one or more don t care conditions. DE 2.2(C) The student will design combinational logic circuit using NAND and NOR logic gates. 4 Days 20 Days 6Days

Third Six Weeks DE 2.2(D) The student will translate a set of design specifications into a functional NAND or NOR combinational logic circuit following a formal design process. DE 2.2(E) The student will be able to compare and contrast the quality of combinational logic designs implemented with AOI, NAND, and NOR logic gates. DE 2.2(F) The student will use Circuit Design Software (CDS) and a Digital Logic Board (DLB) to simulate and prototype NAND and NOR logic circuits. DE 2.3(A) The student will use a seven-segment display in a combinational logic design to display alpha/numeric values. DE 2.3(B) The student will select the correct current limiting resistor and properly wire both common cathode and common anode sevensegment displays. DE 2.3(C) The student will follow a formal design process to translate a set of design specifications for a design containing multiple outputs into a functional combinational logic circuit. DE 2.3(D) The student will design AOI, NAND, & NOR solutions for a logic expression and select the solution that uses the least number of ICs to implement. DE 2.3(E) The student will use Circuit Design Software (CDS) and Digital Logic Board (DLB) to simulate and prototype AOI, NAND, & NOR logic circuits. DE 2.4(A) The student will convert numbers between the hexadecimal or octal number systems and the decimal number system. DE 2.4(B) The student will use XOR and XNOR gates to design binary half-adders and full-adders. DE 2.4(C) The student will use SSI and MSI gates to design and implement binary adders. DE 2.4(D) The student will design electronics displays using sevensegment displays that utilize de-multiplexers. DE 2.4(E) The student will use the two s complement process to add and subtract binary numbers. DE 2.4(F) The student will use Circuit Design Software (CDS) and a Digital Logic Board (DLB) to simulate and prototype specific combinational logic circuits. DE 2.5(A) The student will design combinational logic circuits using a programmable logic device. DE 2.5(B) The student will be able to cite the advantages and disadvantages of programmable logic devices over discrete logic gates. 6 Days 9 Days 7 Days

Fourth Six Weeks DE 2.5(C) The student will use Circuit Design Software (CDS) and a Digital Logic Board (DLB) to simulate and prototype combinational logic designs implemented with programmable logic DE 3.1(A) The student will know the schematic symbols and excitation tables for the D and J/K flip-flops. DE 3.1(B) The student will describe the function of the D and J/K flipflops. DE 3.1(C) The student will describe the function of, and differences between, level sensitive and edge sensitive triggers. DE 3.1(D) The student will describe the function of, and differences between, active high and active low signals. DE 3.1(E) The student will describe the function of, and differences between, a flip-flop s synchronous and asynchronous inputs. DE 3.1(F) The student will draw detailed timing diagrams for the D or J/K flip-flop s Q output in response to a variety of synchronous and asynchronous input conditions. DE 3.1(G) The student will analyze and design introductory flip-flop applications such as event detection circuits, data synchronizers, shift registers, and frequency dividers. DE 3.1(H) The student will use Circuit Design Software (CDS) and a Digital Logic Board (DLB) to simulate and prototype introductory flipflop applications. DE 3.2(A) The student will know the advantages and disadvantage of counters designed using the asynchronous counter method. DE 3.2(B) The student will be able to describe the ripple effect of an asynchronous counter. DE 3.2(C) The student will be able to analyze and design up, down and modulus asynchronous counters using discrete D and J/K flip-flops. DE 3.2(D) The student will be able to analyze and design up, down and modulus asynchronous counters using medium scale integrated (MSI) circuit counters. DE 3.2(E) The student will use Circuit Design Software (CDS) and Digital Logic Board (DLB) to simulate and prototype SSI and MSI asynchronous counters. DE 3.3(A) The student will know the advantages and disadvantage of counters designed using the synchronous counter method. DE 3.3(B) The student will be able to analyze and design up, down and modulus synchronous counters using discrete D and J/K flip-flops. 2 Days 6 Days 14 Days Fifth Six Weeks

DE 3.3(C) The student will be able to analyze and design up, down and modulus synchronous counters using medium scale integrated (MSI) circuit counters. DE 3.3(D) The student will use Circuit Design Software (CDS) and Digital Logic Board (DLB) to simulate and prototype SSI and MSI synchronous counters. DE 3.4(A) The student will be able to describe the components of a state machine. DE 3.4(B) The student will be able to draw a state graph and construct a state transition table for a state machine. DE 3.4(C) The student will be able to derive a state machine s Boolean equations from its state transition table. DE 3.4(D) The student will be able to implement Boolean equations into a functional state machine. DE 3.4(E) The student will describe the two variations of state machines and list the advantages of each. DE 3.4(F) The student will use Circuit Design Software (CDS) and a Digital Logic Board (DLB) to simulate and prototype state machines designs implemented with discrete and programmable logic. DE 4.1(A) The student will create flowcharts to use in programming DE 4.1(B) The student will use the Board of Education to write programs 8Days 20 Days 2Days Sixth Six Weeks DE 4.1(C) The student will create a program that utilizes the Debug screen DE 4.1(D) The student will create programs that use variables DE 4.1(E) The student will create programs that use various loops DE 4.1(F) The student will create programs that use inputs and outputs DE 4.2(A) The student will program a servo motor. DE 4.2(B) The student will program and test an autonomous robot. DE 4.2(C) The student will use mathematics to calculate programming values. DE 4.3(A) The student will design and build a maze course. DE 4.3(B) The student will design and build a timing device with remote triggers. DE 4.3(C) The student will program a microcontroller to guide a robot through a maze. 11 Days 11 Days