Mixed-Signal Gate Array Institut für Mikroelektronik Stuttgart Allmandring 30 a 70569 Stuttgart
This document describes the internal structure of the IMS CHIPS 0.5 µm Mixed Signal Gate Array Family. It is intended for design engineers who plan to use special analog functions and to estimate the performance and resources before starting a design. Index Terms: Mixed-Signal, Structured ASIC. FEATURES Gate Array Technology Analog and Digital Signal Processing 5 V / 3.3 V Operation Different Chip Sizes available Low Development Costs Small Quantities of less than 100 Chips as well as series production FUNCTIONAL DESCRIPTION The mixed signal gate array technology is a sea-of-gates transistor array and provides a 0.5 µm technology with p-substrate, single-well, double-poly and up to 3 metal layers. A number of different sized gate arrays are available. The maximum possible dimensions are (12 x 12) mm 2 with about 300 000 digital micro cells. Gate Array Description Master Digital Micro Cells Analog Micro Cells RAM [64 x 8 bit] I/O-s Dimension [mm²] GFQ010 10 000 40-74 3.0 x 3.3 GFQ032 32 000 74-128 4.7 x 4.7 GFQ060 60 000 101 12 176 5.9 x 5.9 Table 1: Gate Array List 2
ARCHITECTURE The basic structure of the mixed signal gate array is shown in Figure 1. The pad area surrounds the analog and digital cores. All pads can be configured as input, output, bidirectional or power terminals. Analog Analog Digital Digital RAM Figure 1: Block Diagram (left), with on-chip RAM (right) Digital Core Figure 2 (left) shows the basic structure of the digital core. The digital micro cell contains two PMOS and two NMOS transistors. The digital core itself consists of a twodimensional array of abutted digital micro cells, Figure 2 (right). The transistor geometry is fixed for the PMOS (L P =0.55 µm, W P =12.4 µm) and NMOS (L N =0.5 µm, W N =7.6 µm) devices. A two input CMOS NOR or NAND gate or two CMOS inverters can implemented within one digital site. PMOS Poly P-Diff L Cont NMOS W N-Diff Figure 2: Digital Micro Cell (left), two-dimensional array of digital micro cells (right) 3
Analog Core The analog region located in the upper chip region consists of a one-dimensional array of abutted analog micro cells. Capacitance Poly Resistor Area Gate Poly Resistor Area Capacitance Poly Resistor Sheet Resistance Resistance 80 Ω/ 2.82 kω 20 Long Transistors Standard Transistors (NMOS) Long Transistors Gate Poly Resistor Sheet Resistance Resistance NMOS 12 Ω/ 200 Ω 20 PMOS Standard transistors 8.8 µm 1.6 µm 16 x 2 1) 10.5 µm 1.4 µm 16 x 2 1) Standard Transistors (PMOS) Long transistors 1.6 µm 15.0 µm 8 1.6 µm 15.0 µm 4 x 2 2) Long Transistors (PMOS) Small transistors 1.8 µm 0.6 µm 10 x 2 2) 4.2 µm 0.6 µm 10 x 2 2) Small Transistors (NMOS and PMOS) Unit capacitor Capacitance / unit 90 ff 16 Unit Capacitor Area Small transistors 1.8 µm 0.6 µm 5 x 2 1) transistors share gates and one diffusion 2) transistors share one diffusion Small Transistors (NMOS) Figure 3: Analog Micro Cell (left), Device Properties (right) The total resistance of the gate poly resistors is about 4.0 kω per micro-cell whereas the total resistance of the capacitance poly resistors equals 56.5 kω. The total capacitance in the analog micro-cell is 1.44 pf. 4
Cells Each pad cell contains 3 slots of resistors, driver, pull-up / -down, enable, and logic transistors, which are used for ESD protection and output buffering, input pull-up or pull-down and logic function. 3 x 1 NMOS Enable Transistors 3 x 8 NMOS Logic Transistors 3 x 8 PMOS Logic Transistors 3 x 1 PMOS Enable Transistor 3 x 8 PMOS Driver Transistors 3 x PMOS Pull-Up Transistors Gate Poly Resistors 3 x NMOS Pull-Down Transistors Long Transistors 3 x 6 NMOS Driver Transistors Driver transistors Enable transistors Pull-up / down transistors Logic PMOS/NMOS NMOS 24.0 µm 1.4 µm 3) 4) 3 x 6 2.2 µm 0.8 µm 3 x 1 2.0 µm 13 µm 3 x 1 PMOS 24.0 µm 0.8 µm 3 x 8 3) 6.4 µm 0.8 µm 3 x 1 2.2 µm 3.8 µm 3 x 1 3 x 8 3 x 8 3) transistors share one diffusion 4) transistors have asymmetric diffusion areas for better ESD protection Gate poly resistor Sheet Resistance Dimensions Resistance 12 Ω/ 24.4 µm x 6.4 µm 3 x 46 Ω Bond Area (100µm x 100µm) Figure 4: Cell (left), Device Properties (right) Figure 4 illustrates the location of NMOS and PMOS devices which are identical for ll pad types. The pad cell itself consists of 3 identical slots. 5
The upper pad cell area contains a number of different PMOS and NMOS devices. Four transistors share different P- and N-diffusion areas and have a common gate. One transistor pair contains a PMOS transistor with a W/L of 36.6µm/0.8µm, a PMOS with 2.8µm/0.6µm, an NMOS with 5.4µm/0.8µm and an NMOS with 10.8µm/0.8µm. The smaller transistor pair structure contains a PMOS transistor with a W/L of 9.4µm/0.8µm, a PMOS with 18.9µm/0.8µm, an NMOS with 14.7µm/0.8µm and an NMOS with 1.4µm/0.6µm. The special functionality of each pad is given by wiring the devices accordingly. Example The following application shows how the mixed-signal gate array can be used to perform on-the-fly encrypting and decrypting of audio signals, see Figure 5. Figure 5: Functions performed on-chip (right), Final Chip Layout GFQ060 (right) An audio signal is converted on-chip into a 44 100 samples, 8-bit pulse coded signal. The conversion is done with the successive approximation algorithm which uses a clocked comparator and an 8-bit digital to analog converter which itself consists of an operational amplifier, an R2R network and high performance switches. After this the pulse coded signal is encrypted based on the Rijndal algorithm (AES 256). Here 13 iterations with identical transformations are performed. The key, which must be strictly confidential, is stored on-chip in a ROM. In addition the application can store runtime generated keys inside an internal RAM. Chip layout uses IP cores for the analog parts and VHDL synthesis for the digital signal processing. The implementation can be done on GFQ060 which provides SRAM. With this selection the gate count is as follows: 12 800 out of 60 000 digital gates, 5 out of 101 analog sites and 6 out of 176 I/O pins. The chip is operated at 10 MHz. For more details see http://www.mpc.belwue.de/pub/public/workshopband41/mpc_workshopband_41.pdf, p. 3 6
RELATED DOCUMENTS AND AVAILABLE DATA standard cell library catalog for digital and I/O cells data sheets for selected digital and analog IP blocks BSIM3v3 transistor parameter for HSPICE, SPECTRE and LTSPICE simulator GDS File of micro architecture DISCLAMER IMS CHIPS reserves the right to make changes without prior notice to the products contained in this document in order to improve design, performance or reliability. While the information in this document has been carefully checked, no responsibility is assumed for any inaccuracies. Neither is any liability assumed for damage resulting from the use of the information contained within this document. 7
Institut für Mikroelektronik Stuttgart Allmandring 30a, 70569 Stuttgart Tel.: +49 711 21855-0 Fax: +49 711 21855-111 asics@ims-chips.de www.ims-chips.de 167/WP/09_11 8