Status of the design of the TDC for the GTK TDCpix ASIC

Transcription

1 Status of the design of the TDC for the GTK TDCpix ASIC Gianluca Aglieri Rinella, Lukas Perktold DLL design review meeting,

2 Outline Introduction Purpose and objectives Reminder Challenges of design TDC Block diagram and description Status of design Routing of code lines Power distribution

3 Objectives and purpose of this review Check verification methodologies Aspects that might still be overlooked Formal approval by experts of the DLL circuit DLL believed to be finished

4 Reminder of circuit requirements v [au] t [s] Discriminator Hit leading Hit falling 320 MHz ns n-3 n-2 n-1 n n+1 n+2 n+3 Coarse code

5 Challenges of design TDC design tested in the prototype DLL + fine and coarse time stamp registers DLL re-design challenges Detailed by Lukas Fine and coarse registers re-design Parallel readout and 32 to 5 bit encoding of fine codes Reduction of bits of coarse counters Layout Combine DLL, fine code registers and encoders Fit inside the width of one pixel column (300 um) Routing

6 TDCpix block diagram

7 TDCpix block diagram - TDC

8 TDC block diagram x9 Hit Hit arbiter + Hit arbiter Hit arbiter RO control TDC DLL 32 x9 FIFO write FIFO full x9 Coarse register (rise) Coarse Coarse counter Pixelgroup group Pixel Pixel group FIFO FIFO FIFO x9

9 DLL and fine code registers DLL Block diagram Buffers Buffers 32 Floor plan

10 Layout fits column width DLL Buffers Buffers 32

11 Status of DLL DLL (Lukas) Fully characterized Detail documentation State machine Being transferred from the prototype design

12 Fine time stamp registers Existing 32b registers modified No changes to custom building cells (buffers and FFs) Added parallel outputs to layout Layout of power stripes Added explicit sub pins (no use of global nets) Added gate tie downs

13 Time stamp 32to5 encoder block Synthesized from HDL with SoCEncounter, imported into Virtuoso

14 Edge Detector Edge Detector Modification of block from prototype asic One input only, buffering stages added Layout modifications Some of original buffer cells from Sakari have been modified (more compact layout) Option to replace this block with simple repeaters being considered

15 Buffers for DLL wires Buffers DLL fine code lines repeaters Design and characterization by Lukas 32x double inverters Details in Lukas presentation

16 Buffers on DLL wires DLL buffers Buffers Buffers Placed at 1/3 and 2/3 of registers bank height, i.e. wires length

17 Routing of DLL fine code wires Fine code lines Pitch adpater Bias decoupling capacitor 32b Register 32to5 A A' MG Vhigh / vlow Cross section AA' Enc<m-1> vlow vlow DLL<n> vhigh vhigh Enc<m> Enc<m+1> Enc<m+2> Vlow / vhigh / Register circuits vlow vlow DLL<n+1> MQ M3

18 Powering scheme Dedicated power domain for DLL Fine hit registers s Buffers (code repeaters) Edge detectors (hit repeaters) Substrate isolation DLL in a substrate area surrounded by high resistivity undoped region Register bank also isolated Decoupling capacitors

19 Powering scheme diagram BFMOAT vhigh SubDll DLL DLL vlow 11 pf SubReg Fine Fine Fine 11 pf Fine Fine Fine Buffers Buffers Fine Fine Fine Fine Fine Fine Buffers Buffers vhigh Fine Fine Fine Fine Fine Fine vlow 11 pf 11 pf

20 Summary of TDC status Done DLL Fine timestamp registers, s, Edge detectors Routing of DLL lines Interconnection bus To do Replace edge detectors with repeaters Route transmission line for DLL input clock Coarse code generator and registers See concept design by Gianluca Functional and timing models for all blocks Global verification

21 Spare slides

22 DM 3-2 MA / E / Global signals (clk, reset) Ver Hor Power stripes LY / Local routing MG / MQ / M3 M2 M / / / Power stripes Ver Hor Regional routing Local routing Ver Hor Ver Hor

23 Voltage drop on power rails Model including Inductance of bonding wires Input impedance of DLL Resistance and capacitance of minimum size powering stripes Worst case pessimistic assumptions for all estimates and stimulus Decoupling capacitors have sizable effect WITHOUT decoupling capacitors WITH decoupling capacitors