Arithmetic Packages- Introduction

Similar documents
Digital Design with VHDL

VHDL Test Bench Tutorial

Step : Create Dependency Graph for Data Path Step b: 8-way Addition? So, the data operations are: 8 multiplications one 8-way addition Balanced binary

VHDL GUIDELINES FOR SYNTHESIS

ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)

12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr

Binary Adders: Half Adders and Full Adders

LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER

Floating point package user s guide By David Bishop (dbishop@vhdl.org)

Lenguaje VHDL. Diseño de sistemas digitales secuenciales

Digital Design with Synthesizable VHDL

State Machines in VHDL

Using Xilinx ISE for VHDL Based Design

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

The string of digits in the binary number system represents the quantity

The Designer's Guide to VHDL

Quartus II Introduction for VHDL Users

Today. Binary addition Representing negative numbers. Andrew H. Fagg: Embedded Real- Time Systems: Binary Arithmetic

In this example the length of the vector is determined by D length and used for the index variable.

(Refer Slide Time: 00:01:16 min)

if-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z <= A; else Z <= B; end if; end process;

CNC FOR EDM MACHINE TOOL HARDWARE STRUCTURE. Ioan Lemeni

Coding Guidelines for Datapath Synthesis

VHDL programmering H2

Digital Systems Design. VGA Video Display Generation

Sistemas Digitais I LESI - 2º ano

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev Key Design Features. Block Diagram. Generic Parameters.

Life Cycle of a Memory Request. Ring Example: 2 requests for lock 17

Counters & Shift Registers Chapter 8 of R.P Jain

Implementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2)

Digital Design. Assoc. Prof. Dr. Berna Örs Yalçın

Oct: 50 8 = 6 (r = 2) 6 8 = 0 (r = 6) Writing the remainders in reverse order we get: (50) 10 = (62) 8

BINARY CODED DECIMAL: B.C.D.

Modeling Latches and Flip-flops

VGA video signal generation

Computer Science 281 Binary and Hexadecimal Review

16-bit ALU, Register File and Memory Write Interface

The 104 Duke_ACC Machine

(1) /30 (2) /30 (3) /40 TOTAL /100

Hardware Implementation of the Stone Metamorphic Cipher

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann

INTRODUCTION TO DIGITAL SYSTEMS. IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE

ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. Basic Verilog

Designing Digital Circuits a modern approach. Jonathan Turner

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language

An Example VHDL Application for the TM-4

Multipliers. Introduction

Asynchronous counters, except for the first block, work independently from a system clock.

Decimal Number (base 10) Binary Number (base 2)

Sprites in Block ROM

Lecture 2. Binary and Hexadecimal Numbers

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

CSE140 Homework #7 - Solution

CPE 462 VHDL: Simulation and Synthesis

Lab 1: Introduction to Xilinx ISE Tutorial

Lecture 8: Synchronous Digital Systems

Understanding Logic Design

(1) D Flip-Flop with Asynchronous Reset. (2) 4:1 Multiplexor. CS/EE120A VHDL Lab Programming Reference

Let s put together a Manual Processor

Aims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic

Gates, Plexers, Decoders, Registers, Addition and Comparison

EE 261 Introduction to Logic Circuits. Module #2 Number Systems

CS101 Lecture 26: Low Level Programming. John Magee 30 July 2013 Some material copyright Jones and Bartlett. Overview/Questions

Counters are sequential circuits which "count" through a specific state sequence.

Combinational-Circuit Building Blocks

EC313 - VHDL State Machine Example

Binary Division. Decimal Division. Hardware for Binary Division. Simple 16-bit Divider Circuit

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

Asynchronous & Synchronous Reset Design Techniques - Part Deux

Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic

Systems I: Computer Organization and Architecture

DEPARTMENT OF INFORMATION TECHNLOGY

Cascaded Counters. Page 1 BYU

Counters and Decoders

Introduction to Xilinx System Generator Part II. Evan Everett and Michael Wu ELEC Spring 2013

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc

FINITE STATE MACHINE: PRINCIPLE AND PRACTICE

Flip-Flops, Registers, Counters, and a Simple Processor

ASYNCHRONOUS COUNTERS

Architectures and Design Methodologies for Micro and Nanocomputing

To convert an arbitrary power of 2 into its English equivalent, remember the rules of exponential arithmetic:

Activity 1: Using base ten blocks to model operations on decimals

How To Design A Chip Layout

l C-Programming l A real computer language l Data Representation l Everything goes down to bits and bytes l Machine representation Language

A Verilog HDL Test Bench Primer Application Note

Sources: On the Web: Slides will be available on:

Admin. ECE 550: Fundamentals of Computer Systems and Engineering. Last time. VHDL: Behavioral vs Structural. Memory Elements

Start Active-HDL by double clicking on the Active-HDL Icon (windows).

5 Combinatorial Components. 5.0 Full adder. Full subtractor

Shear :: Blocks (Video and Image Processing Blockset )

Modeling Registers and Counters

VHDL Reference Manual

Registers & Counters

Chapter 2 Logic Gates and Introduction to Computer Architecture

EE360: Digital Design I Course Syllabus

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition

A New Paradigm for Synchronous State Machine Design in Verilog

Digital Electronics Detailed Outline

Transcription:

Arithmetic Packages- Introduction It would be very painful if when building a counter we had to think about all the internals We need an adder etc.» How do we build the adder? Would be much better if we could simply say» Add 1 to the current counter value» count <= count + 1 And an (optimal) circuit was automatically generated for us Furthermore, if we work in this way the design is still architecturally independent- A good thing!! 111

Arithmetic Package Overview- I VHDL offers a number of packages which provide common arithmetical functions Addition (+) Subtraction (-) Multiplication (*) Division (/) Comparison (=, >, <, <=, >=, /=) By simply adding in a use clause at the top of your code these become available Synthesis automatically generates the logic required!! 112

Arithmetic Package Overview- II There are a number of different packages that exist for historical reasons STD_LOGIC_ARITH, std_logic_, std_logic_ NUMERIC_STD (IEEE) We will only consider NUMERIC_STD as it is the only standard package which is defined on all commercial synthesis and simulation tools Tools must provide a common set of arithmetical functions Synthesis result (gates and how they are connected) will change with synthesis tool, but functionality will not 113

Declaring Arithmetic Signals & Variables NUMERIC_STD offers 2 data types SIGNED, UNSIGNED These are declared in a similar method to Can be used to declare signals, variables, even ports in an entity UNSIGNED Assumes that only positive values are going to be used Example declaration signal count: (3 downto 0) This creates a signal used for storing values 0 -> 15 114

Declaring Arithmetic Signals & Variables SIGNED 2 s complement form, with MSB used as a sign bit Example declaration signal count: (3 downto 0) Creates a signal used for storing the values -8 -> +7 Integer Signed -8 1000-1 1111 0 0000 +7 0111 115

Representation of Signed/ Un Signed/ Un values are represented using a subset of I.e. 0, 1 in each bit However, cannot perform comparisons, assignments etc. directly with std_logic We need to use conversion functions (see later) 116

Arithmetic Package Functions- I For a detailed list of functions (and their operations) see the program listing from NUMERIC_STD.VHD this is the official IEEE package How do I read the package header? Consider the function Id: A.6 function + (L: UNSIGNED; R: NATURAL) return UNSIGNED UNSIGNED + NATURAL = UNSIGNED 117

Arithmetic Package Functions- II Signed Arithmetic Functions: Function Argument 1 Argument 2 Returns + integer - integer i.e. functions to add/ subtract numbers Note integer as a +ve/ -ve argument for op s 118

Arithmetic Package Functions- III Un Arithmetic Functions: Function Argument 1 Argument 2 Returns + natural - natural i.e. functions to add/ subtract numbers Note natural as a +ve only argument since no notion of sign 119

Arithmetic Package Functions- IV Comparison functions: Function Name Argument 1 Argument 2 Returns = /= Equal Not equal > < Greater than Less than natural boolean >= <= Greater than/equal Less than/equal integer 120

Arithmetic Package Functions- V Resize functions Used for resizing a / value Useful if we want to extract carry bit etc. Function Description Argument 1 Argument 2 Returns resize Resize argument natural (new size) natural (new size) (new size) (new size) Example newvalue = resize(oldvalue, 5) 121

Arithmetic Package Functions- VI Simple conversion functions Used to convert integer/ natural numbers to and from / Function Description Argument 1 Argument 2 Returns to_integer Convert to integer natural integer to_ to_ Convert to Convert to natural integer natural (size) natural (size) (size) (size) 122

Arithmetic Package Functions- VII Conversion to/ from Used to convert and values to and from» Really just copies each bit Function Description Argument Returns Convert to Convert to Convert to Convert to 123

Making the Package Visible At the top of the VHDL source file, the line use ieee.numeric_std.all Library Name Package Name is added This makes the package (functions, data types, etc.) visible 124

Arithmetic Package Example- I Some concrete examples of the use of the arithmetic package! Simple counter Counts up to certain value then resets back Only increments if input inc is set to 1 CLK INC COUNT 0000 0001 0001 0010 0011 0100 0000 No change when inc = 0 125

Arithmetic Package Example- II VHDL process process (CLK,RESET) begin if RESET= 1 then -- reset (asynchronous) internal_count <= 0000 ; elsif CLK EVENT and CLK= 1 then -- clock if inc = 1 then if internal_count = 0100 then else internal_count <= 0000 ; internal_count <= internal_count + 1; end if; else null; end if; end process; 126

Arithmetic Package Example- III Architecture definition use ieee.numeric_std.all; architecture BEHAVIOR of UPCOUNTER is signal internal_count : (3 downto 0); begin -- see previous slide for process count <= (internal_count); end BEHAVIOR; 127

Arithmetic Packages- Conclusion Have given an overview of the numeric package and the functions which it contains These are widely use for counters etc. Can be used to generate many different arithmetic circuits (e.g. multipliers etc.) though it may be better to design these for the given application as the target after synthesis may be inefficient 128